PI7C8150ND Pericom Semiconductor, PI7C8150ND Datasheet
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PI7C8150ND Summary of contents
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PI7C8150 2-Port PCI-to-PCI Bridge 2380 Bering Drive, San Jose, CA 95131 Telephone: 1-877-PERICOM, (1-877-737-4266) Email: Internet: REVISION 1.04 Fax: 408-435-1100 solutions@pericom.com http://www.pericom.com ...
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... Pericom Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use ...
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REVISION HISTORY Date Revision Number 07/16/02 1.01 First Release of Data Sheet 08/06/02 1.02 Removed “TBD” parameters for T 9/4/02 1.03 12/5/02 1.03 03/19/03 1.04 Corrected section reference on p17 from 5.3 to 4.3. Description DELAY Added 256-ball PBGA package ...
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TABLE OF CONTENTS 1 INTRODUCTION ................................................................................................................................ 1 2 SIGNAL DEFINITIONS ..................................................................................................................... 2 2 ................................................................................................................................. 2 IGNAL YPES 2.2 S .......................................................................................................................................... 2 IGNALS 2.2.1 PRIMARY BUS INTERFACE SIGNALS ............................................................................ 2 2.2.3 CLOCK SIGNALS ................................................................................................................. 5 2.2.4 MISCELLANEOUS SIGNALS............................................................................................. 5 ...
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MEMORY ADDRESS DECODING............................................................................................ 31 4.3.1 MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS ......................... 32 4.3.2 PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS ................. 33 4.4 VGA SUPPORT ........................................................................................................................... 34 4.4.1 VGA MODE......................................................................................................................... 34 4.4.2 VGA SNOOP MODE........................................................................................................... 34 5 ...
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SUPPORTED COMMANDS......................................................................................................... 60 13.1 PRIMARY INTERFACE ............................................................................................................. 60 13.2 SECONDARY INTERFACE ....................................................................................................... 61 14 CONFIGURATION REGISTERS................................................................................................ 62 14.1 CONFIGURATION REGISTER.................................................................................................. 62 14.1.1 VENDOR ID REGISTER – OFFSET 00h......................................................................... 63 14.1.2 DEVICE ID REGISTER – OFFSET 00h .......................................................................... 63 14.1.3 ...
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RETRY COUNTER REGISTER – OFFSET 78h .......................................................... 79 14.1.44 PRIMARY MASTER TIMEOUT COUNTER – OFFSET 80h ..................................... 79 14.1.45 SECONDARY MASTER TIMEOUT COUNTER – OFFSET 80h ............................... 79 14.1.46 CAPABILITY ID REGISTER – OFFSET B0h ............................................................. 79 14.1.47 NEXT ...
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Table 4-5. Read Transaction Prefetching_________________________________________________ 17 Table 4-6. Device Number to IDSEL S_AD Pin Mapping____________________________________ 21 Table 4-7. Delayed Write Target Termination Response _____________________________________ 25 Table 4-8. Response to Posted Write Target Termination ____________________________________ 26 Table 4-9. Response to Delayed ...
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This page intentionally left blank. 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION ix March 19, 2003 – Revision 1.04 PI7C8150 ...
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This page intentionally left blank. 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION x March 19, 2003 – Revision 1.04 PI7C8150 ...
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... INTRODUCTION Product Description The PI7C8150 is Pericom Semiconductor’s third-generation PCI-PCI Bridge designed to be fully compliant with the 32-bit, 66MHz implementation of the PCI Local Bus Specification, Revision 2.2. The PI7C8150 supports only synchronous bus transactions between devices on the Primary Bus running at 33MHz to 66MHz and the Secondary Buses operating at either 33MHz or 66MHz ...
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SIGNAL DEFINITIONS 2.1 Signal Types Signal Type STS OD 2.2 Signals Note: Signal names that end with “_L” are active LOW. 2.2.1 PRIMARY BUS INTERFACE SIGNALS Name P_AD[31:0] P_CBE[3:0] P_PAR P_FRAME_L Description Input Only Output ...
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Name Pin # P_IRDY_L 82 P_TRDY_L 83 P_DEVSEL_L 84 P_STOP_L 85 P_LOCK_L 87 P_IDSEL 65 P_PERR_L 88 P_SERR_L 89 P_REQ_L 47 P_GNT_L 46 P_RESET_L 43 P_M66EN 102 3 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Type Description STS Primary IRDY (Active LOW). ...
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SECONDARY BUS INTERFACE SIGNALS Name S_AD[31:0] S_CBE[3:0] S_PAR S_FRAME_L S_IRDY_L S_TRDY_L S_DEVSEL_L S_STOP_L S_LOCK_L Pin # Type Description 206, 204, 203, TS Secondary Address/Data: Multiplexed address and data 201, 200, 198, bus. Address is indicated by S_FRAME_L assertion. 197, ...
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Name S_PERR_L S_SERR_L S_REQ_L[8:0] S_GNT_L[8:0] S_RESET_L S_M66EN S_CFN_L 2.2.3 CLOCK SIGNALS Name P_CLK S_CLKIN S_CLKOUT[9:0] 2.2.4 MISCELLANEOUS SIGNALS Name Pin # Type Description 171 STS Secondary Parity Error (Active LOW): Asserted when a data parity error is detected for data ...
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MSK_IN P_VIO S_VIO BPCCE CFG66 SCAN_EN_H MS0, MS1 2.2.5 GENERAL PURPOSE I/O INTERFACE SIGNALS Name GPIO[3:0] 2.2.6 JTAG BOUNDARY SCAN SIGNALS Name TCK TMS TDO 126 I Secondary Clock Disable Serial Input: This pin is used by PI7C8150 to disable ...
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TDI TRST_L 2.2.7 POWER AND GROUND Name VDD VSS 2.3 PIN LIST – 208-PIN FQFP Table 3-1. Pin list – 208-pin FQFP Pin Number Name 1 VDD 3 S_REQ_L[2] 5 S_REQ_L[4] 7 S_REQ_L[6] 9 S_REQ_L[8] 11 S_GNT_L[1] 13 S_GNT_L[2] 15 ...
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Pin Number Name 55 P_AD[29] 57 P_AD[28] 59 VSS 61 P_AD[25] 63 P_AD[24] 65 P_IDSEL 67 P_AD[23] 69 VDD 71 P_AD[20] 73 P_AD[19] 75 VDD 77 P_AD[16] 79 P_CBE[2] 81 VDD 83 P_TRDY_L 85 P_STOP_L 87 P_LOCK_L 89 P_SERR_L 91 ...
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Pin Number Name 181 VSS 183 S_AD[17] 185 S_AD[18] 187 VSS 189 S_AD[21] 191 S_AD[22] 193 VSS 195 S_AD[24] 197 S_AD[25] 199 VSS 201 S_AD[28] 203 S_AD[29] 205 VSS 207 S_REQ_L[0] 2.4 PIN LIST – 256-BALL PBGA Table 3-2. Pin ...
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Pin Name Number H9 VSS H12 VDD H15 TCK J2 GPIO[2] J5 VDD J8 VSS J11 VSS J14 RESERVED K1 GPIO[0] K4 VDD K7 VSS K10 VSS K13 VDD K16 CFG66/SCAN_EN_H L3 S_CLKOUT[5] L6 VSS L9 VSS L10 VSS L13 ...
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This section provides a summary of PCI transactions performed by PI7C8150. Table 4–1 lists the command code and name of each PCI transaction. The Master and Target columns indicate support for each transaction when PI7C8150 initiates transactions as a master, ...
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PI7C8150 always performs positive address decoding (medium decode) when accepting transactions on either the primary or secondary buses. PI7C8150 never does subtractive decode. 3.4 DATA PHASE The address phase of a PCI transaction is followed by one or more data ...
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The posted write data buffer fills up. When one of the last two events occurs, the PI7C8150 returns a target disconnect to the requesting initiator on this data phase to terminate the transaction. Once the posted write data moves ...
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A delayed write transaction guarantees that the actual target response is returned back to the initiator without holding the initiating bus in wait states. A delayed write transaction is limited to a single DWORD data transfer. When a write transaction ...
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PI7C78150 returns a target disconnect to the initiator when it reaches the aligned address boundaries under conditions shown in Table 4–3. Table 4-3. Write Transaction Disconnect Address Boundaries Type of Transaction Delayed Write Posted Memory Write Posted Memory Write ...
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However, byte enable bits cannot be forwarded for all data phases as is done for the single data phase of the non-prefetchable read transaction. For prefetchable read transactions, PI7C8150 forces all byte enable bits to be turned on for all ...
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Type of Transaction Configuration Read I/O Read Memory Read Memory Read Memory Read Memory Read Line Memory Read Line Memory Read Multiple Memory Read Multiple - does not matter prefetchable or non-prefetchable * don’t care Table 4-5. ...
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PI7C8150 does not initiate any further attempts to read more data. If PI7C8150 is unable to obtain read data from the target after 2 (maximum) attempts, PI7C8150 will report system ...
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PI7C8150 has the capability to post multiple delayed read requests maximum of four in each direction initiator starts a read transaction that matches the address and read command of a read transaction that is already ...
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The bus command is a configuration read or configuration write transaction. ! Lowest two address bits P_AD[1:0] must be 00b. ! Signal P_IDSEL must be asserted. PI7C8150 limits all configuration access to a single DWORD data transfer and returns ...
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Leaves unchanged the function number and register number fields. PI7C8150 asserts a unique address line based on the device number. These address lines may be used as secondary bus IDSEL signals. The mapping of the address lines depends on ...
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The bus number falls in the range defined by the lower limit (exclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register. ! The bus command is a configuration read or ...
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When PI7C8150 initiates the transaction on the target interface, the bus command is changed from configuration write to special cycle. The address and data are for-warded unchanged. Devices that use special cycles ignore the address and decode only the bus ...
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STOP_L asserted with DEVSEL_L and TRDY_L de-asserted. Indicates that target will never be able to complete this transaction. DEVSEL_L must be asserted for at least one cycle during the transaction before the target abort is signaled. 3.8.1 MASTER TERMINATION INITIATED ...
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SERR_L enable bit (bit 8 of command register for secondary bus) are set, PI7C8150 asserts P_SERR_L if the master-abort-on-posted-write is not set. The master- abort-on-posted-write bit is bit 4 of the P_SERR_L event disable register (offset 64h). Note: ...
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After the PI7C8150 makes 2 the target bus, PI7C8150 asserts P_SERR_L if the SERR_L enable bit (bit 8 of command register for the secondary bus) is set and the delayed-write-non-delivery bit is not set. The delayed-write-non-delivery bit is bit 5 ...
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PI7C8150 receives a target abort. 24 PI7C8150 makes 2 Table 4-9. Response to Delayed Read Target Termination Target Termination Normal Target Retry Target Disconnect Target Abort After PI7C8150 makes 2 target bus, PI7C8150 asserts P_SERR_L if the primary SERR_L ...
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For delayed read transactions: ! The transaction is being entered into the delayed transaction queue. ! The read request has already been queued, but read data is not yet available. ! Data has been read from target, but it is ...
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TARGET ABORT PI7C8150 returns a target abort to an initiator when one of the following conditions is met: ! PI7C8150 is returning a target abort from the intended target. ! When PI7C8150 returns a target abort to the initiator, ...
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This section provides information on the I/O address registers and ISA mode. Section 5.4 provides information on the VGA modes. To enable downstream forwarding of I/O transactions, the I/O enable bit must be set in the command register in configuration ...
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After primary bus reset or chip reset, the value of the I/O limit address is reset to 0000 0FFFh. Note: The initial states of the I/O base and I/O limit address registers define an I/O range of 0000 ...
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If any configuration state affecting memory transaction forwarding is changed by a configuration write operation on the primary bus at the same time that memory transactions are ongoing on the secondary bus, response to the secondary bus memory transactions is ...
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PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS Locations accessed in the prefetchable memory address range must have true memory-like behavior and must not exhibit side effects when read. This means that extra reads to a prefetchable memory location must ...
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VGA SUPPORT PI7C8150 provides two modes for VGA support: ! VGA mode, supporting VGA-compatible addressing ! VGA snoop mode, supporting VGA palette forwarding 4.4.1 VGA MODE When a VGA-compatible device exists downstream from PI7C8150, set the VGA mode bit ...
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TRANSACTION ORDERING To maintain data coherency and consistency, PI7C8150 complies with the ordering rules set forth in the PCI Local Bus Specification, Revision 2.2, for transactions crossing the bridge. This chapter describes the ordering rules that control transaction forwarding ...
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PI7C8150 does not collapse sequential write transactions to the same address into a single write transaction—the PCI Local Bus Specification does not permit this combining of transactions. 5.2 GENERAL ORDERING GUIDELINES Independent transactions on primary and secondary buses have ...
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Note: The superscript accompanying some of the table entries refers to any applicable ordering rule listed in this section. Many entries are not governed by these ordering rules; therefore, the implementation can choose whether or not the transactions pass each ...
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The device signaling the interrupt performs a read of the data just written (software). ! The device driver performs a read operation to any register in the interrupting device before accessing data written by the device (software). ! System ...
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The parity error response bit is set in the command register. When PI7C8150 detects an address parity error on the secondary interface, the following events occur the parity error response bit is set in the bridge control ...
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PI7C8150 asserts S_PERR_L two cycles following the data transfer, if the secondary interface parity error response bit is set in the bridge control register. ! PI7C8150 sets the detected parity error bit in the secondary status register. ! PI7C8150 ...
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When PI7C8150 completes the delayed write transaction to the target When a delayed write transaction is normally queued, the address, command, address parity, data, byte enable bits, and data parity are all captured and a target retry is returned ...
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When parity error is forwarded back from the target bus For downstream delayed write transactions, when the parity error is detected on the initiator bus and PI7C8150 has write status to return, the following events occur: ! PI7C8150 first ...
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PI7C8150 completes the transaction normally. 6.2.4 POSTED WRITE TRANSACTIONS During downstream posted write transactions, when PI7C8150 responds as a target, it detects a data parity error on the initiator (primary) bus and the following events occur: ! PI7C8150 asserts ...
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PI7C8150 has not detected the parity error on the primary (initiator) bus which the parity error is not forwarded from the primary bus to the secondary bus. During upstream write transactions, when a data parity error is reported on ...
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Posted Write 1 Delayed Write 0 Delayed Write 0 Delayed Write 0 Delayed Write X = don’t care Table 6–2 shows setting the detected parity error bit in the secondary status register, corresponding to the secondary interface. This bit ...
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Table 6–4 shows setting the data parity detected bit in the status register of secondary interface. This bit is set under the following conditions: ! The PI7C8150 must be a master on the secondary bus. ! The parity error response ...
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Table 6–6 shows assertion of S_PERR_L that is set under the following conditions: ! PI7C8150 is either the target of a write transaction or the initiator of a read transaction on the secondary bus. ! The parity error response bit ...
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P_SERR don’t care 2 The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus. 3 The parity error was detected on the target (primary) bus but not ...
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The master timeout condition has a SERR_L enable bit for that event in the bridge control register and therefore does not have a device-specific disable bit. 7 EXCLUSIVE ACCESS This chapter describes the use of the LOCK_L ...
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Memory read transactions that are a part of the locked transaction sequence are not pre-fetched. When the locked delayed memory read request is queued, PI7C8150 does not ...
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LOCKED TRANSACTION IN UPSTREAM DIRECTION PI7C8150 ignores upstream lock and transactions. PI7C8150 will pass these transactions as normal transactions without lock established. 7.3 ENDING EXCLUSIVE ACCESS After the lock has been acquired on both initiator and target buses, PI7C8150 ...
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PI7C8150 must arbitrate for use of the primary bus when forwarding upstream transactions. Also, it must arbitrate for use of the secondary bus when forwarding downstream transactions. The arbiter for the primary bus resides external to PI7C8150, typically on the ...
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Figure 9–1 shows an example of an internal arbiter where four masters, including PI7C8150, are in ...
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PREEMPTION Preemption can be programmed to be either on or off, with the default to on (offset 4Ch, bit 31=0). Time-to-preempt can be programmed 16, 32 (default is 0) clocks. If ...
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CLOCKS This chapter provides information about the clocks. 9.1 PRIMARY CLOCK INPUTS PI7C8150 implements a primary clock input for the PCI interface. The primary interface is synchronized to the primary clock input, P_CLK, and the secondary interface is synchronized ...
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Write-1-to-set output data field ! Write-1-to-clear output data field ! Write-1-to-set signal output enable control field ! Write-1-to-clear signal output enable control field ! Input data field The bottom four bits of the output enable fields control whether each ...
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The data is input through the dedicated input signal, MSK_IN. The shift register circuitry is not necessary for correct operation of PI7C8150. The shift register can be eliminated, and MSK_IN can be tied LOW to enable all secondary clock outputs ...
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LIVE INSERTION The GPIO[3] pin can be used, along with a live insertion mode bit, to disable transaction forwarding. To enable live insertion mode, the live insertion mode bit in the chip control register must be set to 1, ...
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D3hot D3cold D3cold D0 PME# signals are routed from downstream devices around PCI-to-PCI bridges. PME# signals do not pass through PCI-to-PCI bridges. 12 RESET This chapter describes the primary interface, secondary interface, and chip reset mechanisms. 12.1 PRIMARY INTERFACE RESET ...
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When S_RESET_L is asserted by means of the secondary reset bit, PI7C8150 remains accessible during secondary interface reset and continues to respond to accesses to its configuration space from the primary interface. 12.3 CHIP RESET The chip reset bit in ...
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SECONDARY INTERFACE S_CBE[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Type 1 Configuration Read the target bus is the bridge’s secondary bus: claim and pass through as a ...
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CONFIGURATION REGISTERS PCI configuration defines a 64-byte space (configuration header) to define various attributes of PI7C8150 as shown below. 14.1 CONFIGURATION REGISTER 31-24 Device ID Primary Status Reserved Secondary Latency Timer Secondary Status Memory ...
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Reserved Reserved Secondary Master Timeout Counter Chassis Number Power Management Capabilities Reserved Reserved 14.1.1 VENDOR ID REGISTER – OFFSET 00h Bit Function 15:0 Vendor ID 14.1.2 DEVICE ID REGISTER – OFFSET 00h Bit Function 31:16 Device ID 14.1.3 COMMAND REGISTER ...
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Bus Master 2 Enable Special Cycle 3 Enable Memory Write 4 And Invalidate Enable VGA Palette 5 Snoop Enable Parity Error 6 Response Wait Cycle 7 Control P_SERR_L 8 enable Fast Back-to- 9 Back Enable 15:10 Reserved 14.1.4 STATUS REGISTER ...
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Capabilities List 21 66MHz Capable 22 Reserved 23 Fast Back-to- Back Capable 24 Data Parity Error Detected 26:25 DEVSEL_L timing 27 Signaled Target Abort 28 Received Target Abort 29 Received Master Abort 30 Signaled System Error 31 Detected Parity ...
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Bit Function 7:0 Cache Line Size 14.1.8 PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch Bit Function 15:8 Primary Latency timer 14.1.9 HEADER TYPE REGISTER – OFFSET 0Ch Bit Function 23:16 Header Type 14.1.10 PRIMARY BUS NUMBER REGISTSER – OFFSET 18h ...
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Bit Function 31:24 Secondary Latency Timer 14.1.14 I/O BASE REGISTER – OFFSET 1Ch Bit Function 3:0 32-bit Indicator 7:4 I/O Base Address [15:12] 14.1.15 I/O LIMIT REGISTER – OFFSET 1Ch Bit Function 11:8 32-bit Indicator 15:12 I/O Base Address [15:12] ...
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DEVSEL_L 26:25 timing Signaled Target 27 Abort Received Target 28 Abort Received Master 29 Abort Received System 30 Error Detected Parity 31 Error 14.1.17 MEMORY BASE REGISTER – OFFSET 20h Bit Function 3:0 15:4 Memory Base Address [15:4] 14.1.18 MEMORY ...
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Prefetchable Memory Base Address [31:20] 14.1.20 PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h Bit Function 19:16 64-bit addressing 31:20 Prefetchable Memory Limit Address [31:20] 14.1.21 PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h Bit ...
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I/O Base Address, Upper 16-bits [31:16] 14.1.24 I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h Bit Function 31:0 I/O Limit Address, Upper 16-bits [31:16] 14.1.25 ECP POINTER REGISTER – OFFSET 34h Bit Function 7:0 Enhanced Capabilities Port Pointer ...
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ISA enable R/W Modifies the bridge’s response to ISA I/O addresses, applying only to those addresses falling within the I/O base and limit address registers and within the first 64KB or PCI I/O space. 0: forward all I/O addresses ...
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Secondary Master Timeout 26 Master Timeout Status 27 Discard Timer P_SERR_L enable 31-28 Reserved 14.1.29 DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h Bit Function 0 Reserved 1 Memory Write Disconnect Control 3:2 Reserved 4 Secondary Bus Prefetch Disable ...
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Test Mode For All Counters at P and S1 15:11 Reserved 14.1.30 ARBITER CONTROL REGISTER – OFFSET 40h Bit Function 24:16 Arbiter Control 25 Priority of Secondary Interface 31:26 Reserved 14.1.31 EXTENDED CHIP CONTROL REGISTER – OFFSET 48h Bit ...
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UPSTREAM MEMORY CONTROL REGISTER – OFFSET 48h Bit Function Upstream ( Memory Base and Limit Enable 31:17 Reserved 14.1.33 SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER – OFFSET 4Ch Bit Function Secondary bus arbiter 31:28 preemption contorl ...
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Upstream 31:20 Memory Limit Address 14.1.36 UPSTREAM ( MEMORY BASE UPPER 32-BITS REGISTER – OFFSET 54h Bit Function Upstream 31:0 Memory Base Address 14.1.37 UPSTREAM ( MEMORY LIMIT UPPER 32-BITS REGISTER – ...
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Master Abort On 4 Posted Write Delayed Write 5 Non-Delivery Delayed Read – Data From Target 7 Reserved 14.1.39 GPIO DATA AND CONTROL REGISTER – OFFSET 64h Bit Function GPIO Output 11:8 Write-1-to-Clear GPIO Output 15:12 Write-1-to-Set GPIO ...
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SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h Bit Function 1:0 Clock 0 disable 3:2 Clock 1 disable 5:4 Clock 2 disable 7:6 Clock 3 disable 8 Clock 4 disable 9 Clock 5 disable 10 Clock 6 disable 11 Clock ...
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PORT OPTION REGISTER – OFFSET 74h Bit Function 0 Reserved Primary MEMR 1 Command Alias Enable Primary MEMW 2 Command Alias Enable Secondary MEMR 3 Command Alias Enable Secondary MEMW 4 Command Alias Enable 8:5 Reserved Enable Long 9 ...
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Enable Primary 11 To Hold Request Longer 15:12 Reserved 14.1.43 RETRY COUNTER REGISTER – OFFSET 78h Bit Function 31:0 Retry Counter 14.1.44 PRIMARY MASTER TIMEOUT COUNTER – OFFSET 80h Bit Function 15:0 Primary Timeout 14.1.45 SECONDARY MASTER TIMEOUT COUNTER – ...
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NEXT POINTER REGISTER – OFFSET B0h Bit Function 15:8 Next Pointer 14.1.48 SLOT NUMBER REGISTER – OFFSET B0h Bit Function Expansion Slot 20:16 Number 21 First in Chassis 23:22 Reserved 14.1.49 CHASSIS NUMBER REGISTER – OFFSET B0h Bit Function ...
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D1 Power State 25 Support D2 Power State 26 Support 31:27 PME# Support 14.1.53 POWER MANAGEMENT DATA REGISTER – OFFSET E0h Bit Function 1:0 Power State 7:2 Reserved 8 PME# Enable 12:9 Data Select 14:13 Data Scale 15 PME status ...
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BRIDGE BEHAVIOR A PCI cycle is initiated by asserting the FRAME_L signal bridge, there are a number of possibilities. Those possibilities are summarized in the table below: 15.1 BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES Initiator Master on ...
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Again, the PAR signal corresponds to read data from the previous data phase cycle. 15.2.3 REPORTING PARITY ERRORS For all address phases parity error is detected, the error should be reported on the P_SERR_L signal by ...
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This mode of operation is valuable for design debugging and fault diagnosis since it permits examination ...
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The instruction determines the test to be performed, the test data register to be accessed, or both. The IR is two bits wide. When the IR is selected, the most significant bit is connected to TDI, and the least significant ...
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The PI7C8150 contains two test data registers (bypass and boundary-scan). Each test data register selected by the TAP controller is connected serially between TDI and TDO. TDI is connected to the test data register’s most significant bit. TDO is connected ...
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For greater detail on the behavior of the TAP controller, test logic in each controller state and the state machine and public instructions, refer to the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture document (available from the IEEE). ...
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Boundary-Scan Pin Name Register Number 55 S_REQ_L[6] 56 S_REQ_L[7] 57 S_REQ_L[8] 58 S_GNT_L[0] 59 S_GNT_L[ S_GNT_L[2] 62 S_GNT_L[3] 63 S_GNT_L[4] 64 S_GNT_L[5] 65 S_GNT_L[6] 66 S_GNT_L[7] 67 S_GNT_L[8] 68 S_CLKIN 69 S_RESET_L 70 S_CFN_L 71 GPIO[3] 72 GPIO[2] ...
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Boundary-Scan Pin Name Register Number 117 118 P_LOCK_L 119 P_PERR_L 120 P_SERR_L 121 P_PAR 122 P_CBE[1] 123 P_AD[15] 124 P_AD[14] 125 P_AD[13] 126 P_AD[12] 127 P_AD[11] 128 P_AD[10] 129 P_M66EN 130 P_AD[9] 131 P_AD[8] 132 P_CBE[0] 133 P_AD[7] 134 P_AD[6] ...
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ELECTRICAL AND TIMING SPECIFICATIONS 17.1 MAXIMUM RATINGS (Above which the useful life may be impaired. For user guidelines, not tested). Storage Temperature Ambient Temperature with Power Applied Supply Voltage to Ground Potentials (AV Voltage at Input Pins Note: Stresses ...
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AC SPECIFICATIONS Figure 17-1. PCI Signal Timing Measurement Conditions Symbol Parameter Tsu Input setup time to CLK – bused signals Tsu(ptp) Input setup time to CLK – point-to-point Th Input signal hold time from CLK Tval CLK to signal ...
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TIMING Symbol Parameter T SKEW among S_CLKOUT[9:0] SKEW T DELAY between PCLK and S_CLKOUT[9:0] DELAY T P_CLK, S_CLKOUT[9:0] cycle time CYCLE T P_CLK, S_CLKOUT[9:0] HIGH time HIGH T P_CLK, S_CLKOUT[9:0] LOW time LOW 17.6 POWER CONSUMPTION Parameter Power ...
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... PBGA PACKAGE DIAGRAM Figure 18-2. 256-ball PBGA Package Outline Thermal characteristics can be found on the web: 18.3 PART NUMBER ORDERING INFORMATION Part Number PI7C8150MA PI7C8150MA-33 PI7C8150ND PI7C8150ND-33 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION http://www.pericom.com/packaging/mechanicals.php Speed Pin – Package 66MHz 208 – FQFP 33MHz 208 – ...
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PCI-TO-PCI BRIDGE ADVANCE INFORMATION NOTES: 94 March 19, 2003 – Revision 1.04 PI7C8150 ...
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PCI-TO-PCI BRIDGE ADVANCE INFORMATION NOTES: 95 March 19, 2003 – Revision 1.04 PI7C8150 ...
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PCI-TO-PCI BRIDGE ADVANCE INFORMATION 96 March 19, 2003 – Revision 1.04 PI7C8150 ...