ADBM-A350-200 Avago Technologies US Inc., ADBM-A350-200 Datasheet - Page 17

• Manufacturer Part Number: ADBM-A350-200
• Description: Vigor Colossus OFN Module
• Manufacturer: Avago Technologies US Inc.

Specifications of ADBM-A350-200

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Start and St op of Synchronous Operation
The host initiates and terminates all data transfers. Data transfers are initiated by driving SDA from high to low while
holding SCL high. Data transfers are terminated by driving SDA from low to high while SCL is held high.
Figure 14. TWI Start and Stop operation
Acknowle dge/Not Acknowledge Bit
After a start condition, a single acknowledge/not acknowledge bit follows each Eight-bit data packet. The device
receiving the data drives the acknowledge/not acknowledge signal on SDA. Acknowledge (ACK) is defi ned as 0 and not
acknowledge (NAK) is defi ned as 1.
Packet Formats
Read and write operations between the host and the ADBM-A350 use three types of host driven packets and one type of
ADBM-A350 driven packet. All packets are eight bits long with the most signifi cant bit fi rst, followed by an acknowledge
bit.
Slave Device Address (DA)
Command packets contain a 7-bit ADBM-A350 device address and an active low read/write bit (R/W).
Register Address Packets (RA)
The address packets contain an auto-increment (ai) bit and a 7-bit address. If the ‘ai’ bit is set, the slave will process data
from successive addresses in successive bytes. For example, registers 0x01, 0x02, and 0x03 can be written by setting
the ‘ai’ bit to one with address 0x01. The host would send three bytes of data, and the host would terminate with a P
condition.
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SDA driven
SCL driven
increment=1,
increment=0
by host
by host
First bit of
First bit of
increment
packet
packet
DA[6]
Auto
Auto
No
START Condition
SDA falls while
SCL is high
RA[6]
DA[5]
RA[5]
DA[4]
Device Address
RA[4]
DA[3]
Register Address
RA[3]
DA[2]
RA[2]
DA[1]
SDA rises while
SCL is high
STOP Condition
RA[1]
DA[0]
Last bit of
Last bit of
Write = 0
Read = 1
packet
RA[0]
packet
R/W