ADBM-A350-200 Avago Technologies US Inc., ADBM-A350-200 Datasheet - Page 16

• Manufacturer Part Number: ADBM-A350-200
• Description: Vigor Colossus OFN Module
• Manufacturer: Avago Technologies US Inc.

Specifications of ADBM-A350-200

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Two – Wire Interface (TWI)
ADBM-A350 uses a two-wire serial control interface compatible with I2C. The parameters are listed below.
TWI Specifi cations
Electrical Characteristics over recommended operating conditions. Typical values at 25° C, VDD = 1.8 V.
Notes:
1. All values referred to V
2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
3. The maximum has t
4. C
The ADBM-A350 responds to one of the following select-
able slave device addresses depending on the IO_MOSI_
A0 and IO_NCS_A1 input pin state. These pins should be
set to avoid confl ict with any other devices that might be
sharing the bus.
Table 1. TWI slave address
16
Parameter
SCL clock frequency
Hold time (repeated) START condition. After this period,
the fi rst clock pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Set up time for a repeated START condition
Data hold time
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set up time for STOP condition
Bus free time between a STOP and START condition
Capacitive load for each bus line
Noise margin at the LOW level for each connected device
(including hysteresis)
Noise margin at the HIGH level for each connected device
(including hysteresis)
A0
0
0
1
1
region of the falling edge of SCL.
B
= total capacitance of one bus line in pF.
HD_DAT
A1
0
1
0
1
IHMIN
only to be met if the device does not stretch the LOW period (t
and V
ILMAX
levels.
Slave Address (Hex)
33
3b
53
57
Symbol
fscl
t
t
t
t
t
t
t
t
t
t
C
V
V
HD_STA
LOW
HIGH
SU_STA
HD_DAT
SU_DAT
r
f
SU_STO
BUF
NL
NH
b
Serial Transfer Clock and Serial Data signals
The serial control interface uses two signals: a serial
transfer clock (SCL) signal and a serial data (SDA) signal.
Always driven by the master, SCL synchronizes the serial
transmission of data bits on SDA. The frequency of SCL
may vary throughout a transfer, as long as the timing is
greater than the minimum timing.
SDA is bi-directional. The host (master) can read from or
write to the ADBM-A350. The host (typically a microcon-
troller) drives SCL and SDA in a write operation or request-
ing information from the ADBM-A350. The ADBM-A350
drives the SDA only under two conditions. First, when re-
sponding with an acknowledge (ACK) bit after receiving
data from the host, or second, when sending data to the
host at the host’s request. Data is sent in Eight-bit packets.
Minimum
0.6
1.0
0.6
0.6
0
100
20+0.1C
20+0.1C
0.6
1.3
–
0.1 VDD
0.2 VDD
(2)
LOW
b
b (4)
) of the SCL signal.
(4)
IHMIN
Maximum
400
–
–
–
–
0.9
–
300
300
–
–
400
–
of the SCL signal) to bridge the undefi ned
(3)
Units
kHz
s
s
s
s
s
ns
ns
ns
s
s
pF
V
V
Notes