TWR-K53N512-KIT Freescale Semiconductor, TWR-K53N512-KIT Datasheet - Page 37

• Manufacturer Part Number: TWR-K53N512-KIT
• Description: TWR-K53N512 Dev Kit
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr
• Type: MCUr

Specifications of TWR-K53N512-KIT

• Kit Contents: TWR-K53N512 - 32bit MCU Module With MK53N512CMD100 & TWRPI-SLCD Daughter Card, DVD With IDE Software
• Mcu Supported Families: K50
• Kit Features: MK53N512CMD100 MAPBGA 144 Pins MCU, Tower
• Rohs Compliant: Yes
• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Tower System

1. Resumes normal run mode operation by executing the LLWU interrupt service routine.
2. Follows the reset flow with the LLWU interrupt flag set for the NVIC.
Freescale Semiconductor, Inc.
Leakage Stop)
Wait) -via WFI
Stop)-via WFI
Low Leakage
Low Leakage
Low Leakage
BAT (backup
VLLS3 (Very
VLLS2 (Very
VLLS1 (Very
VLPW (Very
battery only)
VLPR (Very
VLPS (Very
Chip mode
Low Power
Low Power
Low Power
LLS (Low
Stop3)
Stop2)
Stop1)
Run)
On-chip voltage regulator is in a low power mode that supplies only
enough power to run the chip at a reduced frequency. Reduced
frequency Flash access mode (1 MHz); LVD off; internal oscillator
provides a low power 2 MHz source for the core, the bus and the
peripheral clocks.
Same as VLPR but with the core in sleep mode to further reduce
power; NVIC remains sensitive to interrupts (FCLK = ON). On-chip
voltage regulator is in a low power mode that supplies only enough
power to run the chip at a reduced frequency.
Places chip in static state with LVD operation off. Lowest power mode
with ADC and pin interrupts functional. Peripheral clocks are stopped,
but LPTimer, RTC, CMP, TSI, DAC can be used. NVIC is disabled
(FCLK = OFF); AWIC is used to wake up from interrupt. On-chip
voltage regulator is in a low power mode that supplies only enough
power to run the chip at a reduced frequency. All SRAM is operating
(content retained and I/O states held).
State retention power mode. Most peripherals are in state retention
mode (with clocks stopped), but LLWU, LPTimer, RTC, CMP, TSI,
DAC can be used. NVIC is disabled; LLWU is used to wake up.
NOTE: The LLWU interrupt must not be masked by the interrupt
All SRAM is operating (content retained and I/O states held).
Most peripherals are disabled (with clocks stopped), but LLWU,
LPTimer, RTC, CMP, TSI, DAC can be used. NVIC is disabled; LLWU
is used to wake up.
SRAM_U and SRAM_L remain powered on (content retained and I/O
states held).
Most peripherals are disabled (with clocks stopped), but LLWU,
LPTimer, RTC, CMP, TSI, DAC can be used. NVIC is disabled; LLWU
is used to wake up.
SRAM_L is powered off. A portion of SRAM_U remains powered on
(content retained and I/O states held).
Most peripherals are disabled (with clocks stopped), but LLWU,
LPTimer, RTC, CMP, TSI, DAC can be used. NVIC is disabled; LLWU
is used to wake up.
All of SRAM_U and SRAM_L are powered off. The 32-byte system
register file and the 32-byte VBAT register file remain powered for
customer-critical data.
The chip is powered down except for the VBAT supply. The RTC and
the 32-byte VBAT register file for customer-critical data remain
powered.
Description
Table 7. Chip power modes (continued)
controller to avoid a scenario where the system does not fully
exit stop mode on an LLS recovery.
K50 Family Product Brief, Rev. 8, 5/2011
Sleep Deep
Sleep Deep
Sleep Deep
Sleep Deep
Sleep Deep
Core mode
Sleep
Run
Off
Wakeup Reset
Wakeup Reset
Wakeup Reset
Power modes
Sequence
Power-up
Interrupt
recovery
Interrupt
Interrupt
Interrupt
Wakeup
method
Normal
1
37
2
2
2