TWR-K53N512-KIT Freescale Semiconductor, TWR-K53N512-KIT Datasheet - Page 34

• Manufacturer Part Number: TWR-K53N512-KIT
• Description: TWR-K53N512 Dev Kit
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr
• Type: MCUr

Specifications of TWR-K53N512-KIT

• Kit Contents: TWR-K53N512 - 32bit MCU Module With MK53N512CMD100 & TWRPI-SLCD Daughter Card, DVD With IDE Software
• Mcu Supported Families: K50
• Kit Features: MK53N512CMD100 MAPBGA 144 Pins MCU, Tower
• Rohs Compliant: Yes
• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Tower System

Communication interfaces
4.5.7.6 Inter-Integrated Circuit (I
4.5.7.7 UART
4.5.7.8 Secure Digital Host Controller (SDHC)
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• Compatible with I
• Up to 100 kbps with maximum bus loading
• Multi-master operation
• Software programmable for one of 64 different serial clock frequencies
• Programmable slave address and glitch input filter
• Interrupt or DMA driven byte-by-byte data transfer
• Arbitration lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• Bus busy detection broadcast and 10-bit address extension
• Address matching causes wake-up when processor is in low power mode
• Support for ISO 7816 protocol for interfacing with smartcards
• Full-duplex operation
• Standard mark/space non-return-to-zero (NRZ) format
• 13-bit baud rate selection with fractional divide of 32
• Programmable 8-bit or 9-bit data format
• Separately enabled transmitter and receiver
• Programmable transmitter output polarity
• Programmable receive input polarity
• 13-bit break character option
• 11-bit break character detection option
• Parameterizable buffer support for one dataword for each transmit and receive
• Independent FIFO structure for transmit and receive
• Two receiver wakeup methods:
• Address match feature in receiver to reduce address mark wakeup ISR overhead
• Interrupt or DMA driven operation
• Receiver framing error detection
• Hardware parity generation and checking
• 1/16 bit-time noise detection
• Compatible with the following specifications:
• Designed to work with CE-ATA, SD Memory, miniSD Memory, SDIO, miniSDIO, SD Combo, MMC, MMCplus, and
• SD bus clock frequency up to 50 MHz
• Supports 1-/4-bit SD and SDIO modes, 1-/4-/8-bit MMC modes, 1-/4-/8-bit CE-ATA devices
• Up to 200 Mbps data transfer for SD/SDIO cards using four parallel data lines
RS-MMC cards
• Idle line wakeup
• Address mark wakeup
• SD Host Controller Standard Specification, Version 2.0
• MultiMediaCard System Specification, Version 4.2
• SD Memory Card Specification, Version 2.0
• SDIO Card Specification, Version 2.0
• CE-ATA Card Specification, Version 1.0
advanced DMA support
cards
2
C bus standard and SMBus Specification Version 2 features
K50 Family Product Brief, Rev. 8, 5/2011
(http://www.sdcard.org
(http://www.sdcard.org
2
C)
(http://www.sdcard.org
(http://www.mmca.org
(http://www.sdcard.org
)
)
), supporting high capacity SD memory
)
) with test event register and
Freescale Semiconductor, Inc.