TWR-K53N512-KIT Freescale Semiconductor, TWR-K53N512-KIT Datasheet - Page 26

• Manufacturer Part Number: TWR-K53N512-KIT
• Description: TWR-K53N512 Dev Kit
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr
• Type: MCUr

Specifications of TWR-K53N512-KIT

• Kit Contents: TWR-K53N512 - 32bit MCU Module With MK53N512CMD100 & TWRPI-SLCD Daughter Card, DVD With IDE Software
• Mcu Supported Families: K50
• Kit Features: MK53N512CMD100 MAPBGA 144 Pins MCU, Tower
• Rohs Compliant: Yes
• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Tower System

System modules
4.5.2
4.5.2.1 Power Management Control Unit (PMC)
4.5.2.2 DMA Channel Multiplexer (DMA MUX)
4.5.2.3 DMA Controller
4.5.2.4 Watchdog Timer (WDOG)
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• Instrumentation Trace Macrocell (ITM) with the following functionality:
• Embedded Trace Macrocell (ETM) supports instruction trace
• CoreSight
• Test Port Interface Unit (TPIU) acts as a bridge between ITM or ETM and an off-chip Trace Port Analyzer
• Flash Patch and Breakpoints (FPB) implements hardware breakpoints and patches code and data from code space to
• Separate digital (regulated) and analog (referenced to digital) supply outputs
• Programmable power saving modes
• No output supply decoupling capacitors required
• Available wake-up from power saving modes via RTC and external inputs
• Integrated Power-on Reset (POR)
• Integrated Low Voltage Detect (LVD) with reset (brownout) capability
• Selectable LVD trip points
• Programmable Low Voltage Warning (LVW) interrupt capability
• Buffered bandgap reference voltage output
• Factory programmed trim for bandgap and LVD
• 1 kHz Low Power Oscillator (LPO)
• 16 independently selectable DMA channel routers
• 4 periodic trigger sources available
• Each channel router can be assigned to 1 of 64 possible peripheral DMA sources
• Up to 32 fully programmable channels with 32-byte transfer control descriptors
• Data movement via dual-address transfers for 8-, 16-, 32- and 128-bit data values
• Programmable source, destination addresses, transfer size, support for enhanced address modes
• Support for major and minor nested counters with one request and one interrupt per channel
• Support for channel-to-channel linking and scatter/gather for continuous transfers with fixed priority and round-robin
• Independent, configurable clock source input
program flow with standard JTAG tools.
system space
channel arbitration
• several counters or a data match event trigger for performance profiling
• configurable to emit PC samples at defined intervals or to emit interrupt event information
• Software trace - writes directly to ITM stimulus registers can cause packets to be emitted
• Hardware trace - packets generated by DWT are emitted by ITM
• Time stamping - emitted relative to packets
System modules
™
Embedded Trace Buffer (ETB) is a memory-mapped buffer to store trace data. Allows reconstruction of
K50 Family Product Brief, Rev. 8, 5/2011
Freescale Semiconductor, Inc.