TWR-K53N512-KIT Freescale Semiconductor, TWR-K53N512-KIT Datasheet - Page 31

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TWR-K53N512-KIT

Manufacturer Part Number
TWR-K53N512-KIT
Description
TWR-K53N512 Dev Kit
Manufacturer
Freescale Semiconductor
Series
Kinetisr
Type
MCUr
Datasheets

Specifications of TWR-K53N512-KIT

Kit Contents
TWR-K53N512 - 32bit MCU Module With MK53N512CMD100 & TWRPI-SLCD Daughter Card, DVD With IDE Software
Mcu Supported Families
K50
Kit Features
MK53N512CMD100 MAPBGA 144 Pins MCU, Tower
Rohs Compliant
Yes
Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Tower System
4.5.6.2 FlexTimers (FTM)
4.5.6.3 Programmable Interrupt Timers (PITs)
4.5.6.4 Low Power Timer
Freescale Semiconductor, Inc.
• Up to eight DAC interval triggers
• Up to eight pulse outputs (pulse-out's)
• Selectale FTM source clock
• Programmable prescaler
• 16-bit counter supporting free-running or initial/final value, and countin is up or up-down
• Input capture, output compare, and edge-aligned and center-aligned PWM modes
• Input capture and output compare modes
• Operation of FTM channels as pairs with equal outputs, pairs with complimentary outputs, or independent channels
• Deadtime insertion is available for each complementary pair
• Generation of hardware triggers
• Software control of PWM outputs
• Up to 4 fault inputs for global fault control
• Configurable channel polarity
• Programmable interrupt on input capture, reference compare, overflowed counter, or detected fault condition
• Quadrature decoder with input filters, relative position counting, and interrupt on position count or capture of position
• DMA support for FTM events
• Global time base mode shares single time base across multiple FTM instances
• Up to 4 general purpose interrupt timers
• Up to 4 interrupt timers for triggering ADC conversions
• 32-bit counter resolution
• Clocked by system clock frequency
• DMA support
• Operation as timer or pulse counter
• Selectable clock for prescaler/glitch filter
with independent outputs
count on external event
• Optional back-to-back mode operation, which enables the ADC conversions complete to trigger the next PDB
• One programmable delay interrupt
• One sequence error interrupt
• One channel flag and one sequence error flag per pre-trigger
• DMA support
• One interval trigger output per DAC
• One 16-bit delay interval register per DAC trigger output
• Optional bypass the delay interval trigger registers
• Optional external triggers
• Pulse-out's can be enabled or disabled independently.
• Programmable pulse width
• 1 kHz internal LPO
• External low power crystal oscillator
channel
K50 Family Product Brief, Rev. 8, 5/2011
Timers
31

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