MAX1358BETL+ Maxim Integrated Products, MAX1358BETL+ Datasheet - Page 24

IC DAS 16BIT 40-TQFN

MAX1358BETL+

Manufacturer Part Number
MAX1358BETL+
Description
IC DAS 16BIT 40-TQFN
Manufacturer
Maxim Integrated Products
Type
Data Acquisition System (DAS)r
Datasheet

Specifications of MAX1358BETL+

Resolution (bits)
16 b
Sampling Rate (per Second)
21.84k
Data Interface
Serial
Voltage Supply Source
Analog and Digital
Voltage - Supply
1.8 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
40-TQFN Exposed Pad
Number Of Converters
2
Resolution
16 bit
Interface Type
Serial (4-Wire, SPI, QSPI, Microwire)
Voltage Reference
1.25 V
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.8 V
Maximum Power Dissipation
2051.3 mW
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Input Voltage
1.8 V to 3.6 V
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
24
PIN
10
11
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
______________________________________________________________________________________
32KOUT
CLK32K
NAME
UPIO2
UPIO3
UPIO4
DOUT
32KIN
SNO1
SCM1
SNO2
SCM2
SCLK
SNC1
SNC2
OUT1
IN1+
CLK
IN1-
DIN
INT
Clock Output. Default is 2.457MHz output clock for the μC.
User-Programmable Input/Output 2. See the UPIO2_CTRL Register section for functionality.
User-Programmable Input/Output 3. See the UPIO3_CTRL Register section for functionality.
User-Programmable Input/Output 4. See the UPIO4_CTRL Register section for functionality.
Serial-Data Output. Data is clocked out on SCLK’s falling edge. High impedance when
UPIO/SPI pass-through mode is enabled, DOUT mirrors the state of UPIO1.
Serial-Clock Input. Clocks data in and out of the serial interface.
Serial-Data Input. Data is clocked in on SCLK’s rising edge.
Active-Low Chip-Select Input. Data is not clocked into DIN unless
impedance. High impedance when
mirrors the state of UPIO1.
Programmable Active-High/Low Interrupt Output. ADC, UPIO wake-up, alarm, and voltage-monitor events.
32kHz Clock Input/Output. Outputs 32kHz clock for the μC. Can be programmed as an input by enabling
the IO32E bit to accept an external 32kHz input clock. The RTC, PWM, and watchdog timer always use the
internal 32kHz clock derived from the 32kHz crystal.
Active-Low, Open-Drain Reset Output. Remains low while DV
stays low for a timeout period (t
when the watchdog timer times out and holds low during POR until the 32kHz oscillator stabilizes.
32kHz Crystal Output. Connect an external 32kHz watch crystal between 32KIN and 32KOUT.
32kHz Crystal Input. Connect an external 32kHz watch crystal between 32KIN and 32KOUT.
Analog Switch 1 Normally Open Terminal. Analog input to mux.
Analog Switch 1 Common Terminal. Analog input to mux.
Analog Switch 1 Normally Closed Terminal. Analog input to mux (open on POR).
Analog Switch 2 Normally Open Terminal. Analog input to mux.
Analog Switch 2 Common Terminal. Analog input to mux (open on POR).
Analog Switch 2 Normally Closed Terminal. Analog input to mux.
Amplifier 1 Output. Analog input to mux.
Amplifier 1 Inverting Input. Analog input to mux.
Amplifier 1 Noninverting Input
DSLP
) after DV
is high; when UPIO/SPI pass-through mode is enabled, DOUT
DD
FUNCTION
rises above the 1.8V threshold.
DD
is below the 1.8V voltage threshold and
is low. When
Pin Description
is high, DOUT is high
also pulses low
is high, when

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