AD7927BRUZ Analog Devices Inc, AD7927BRUZ Datasheet - Page 2

• Manufacturer Part Number: AD7927BRUZ
• Description: IC ADC 12BIT 8CH 200KSPS 20TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7927BRUZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 12
• Sampling Rate (per Second): 200k
• Number Of Converters: 1
• Power Dissipation (max): 7.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 12bit
• Sampling Rate: 200kSPS
• Input Channel Type: Single Ended
• Supply Voltage Range - Analog: 2.7V To 5.25V
• Supply Current: 1.5mA
• Number Of Elements: 1
• Resolution: 12Bit
• Architecture: SAR
• Sample Rate: 200KSPS
• Input Polarity: Unipolar
• Input Type: Voltage
• Rated Input Volt: 2.5/5V
• Differential Input: No
• Power Supply Requirement: Analog and Digital
• Single Supply Voltage (typ): 3/5V
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.25V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 7.5mW
• Differential Linearity Error: -0.9LSB/1.5LSB
• Integral Nonlinearity Error: ±1LSB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: TSSOP
• Input Signal Type: Single-Ended
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7927CBZ - BOARD EVALUATION FOR AD7927
• Lead Free Status / Rohs Status: Compliant

AD7927–SPECIFICATIONS
Parameter
DYNAMIC PERFORMANCE
DC ACCURACY
ANALOG INPUT
REFERENCE INPUT
LOGIC INPUTS
LOGIC OUTPUTS
Signal-to-(Noise + Distortion) (SINAD)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
Intermodulation Distortion (IMD)
Aperture Delay
Aperture Jitter
Channel-to-Channel Isolation
Full Power Bandwidth
Resolution
Integral Nonlinearity
Differential Nonlinearity
0 V to REF
0 V to 2 ¥ REF
Input Voltage Ranges
DC Leakage Current
Input Capacitance
REF
DC Leakage Current
REF
Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C
Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage Current
Floating-State Output Capacitance
Output Coding
(SFDR)
Second Order Terms
Third Order Terms
Offset Error
Offset Error Match
Gain Error
Gain Error Match
Positive Gain Error
Positive Gain Error Match
Zero Code Error
Zero Code Error Match
Negative Gain Error
Negative Gain Error Match
IN
IN
Input Voltage
Input Impedance
2
IN
Input Range
IN
2
IN
Input Range
IN
INL
INH
3
OL
OH
2
2
2
2
3
2
B Version
70
69
70
–77
–73
–78
–76
–90
–90
10
50
–82
8.2
1.6
12
± 1
–0.9/+1.5
± 8
± 0.5
± 1.5
± 0.5
± 1.5
± 0.5
± 8
± 0.5
± 1
± 0.5
0 to REF
0 to 2 ¥ REF
± 1
20
± 1
36
0.7 ¥ V
0.3 ¥ V
± 1
10
V
0.4
± 1
10
Straight (Natural) Binary
Twos Complement
2.5
DRIVE
(AV
otherwise noted.)
– 0.2
DRIVE
DRIVE
DD
IN
1
= V
IN
DRIVE
Unit
dB min
dB min
dB min
dB max
dB max
dB max
dB max
dB typ
dB typ
ns typ
ps typ
dB typ
MHz typ
MHz typ
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
V
V
mA max
pF typ
V
mA max
kW typ
V min
V max
mA max
pF max
V min
V max
mA max
pF max
–2–
= 2.7 V to 5.25 V, REF
Test Conditions/Comments
f
@ 5 V
@ 3 V Typically 70 dB
@ 5 V Typically –84 dB
@ 3 V Typically –77 dB
@ 5 V Typically –86 dB
@ 3 V Typically –80 dB
fa = 40.1 kHz, fb = 41.5 kHz
f
@ 3 dB
@ 0.1 dB
Guaranteed No Missed Codes to 12 Bits
Straight Binary Output Coding
Typically ± 0.5 LSB
–REF
Twos Complement Output Coding
Typically ± 0.8 LSB
RANGE Bit Set to 1
RANGE Bit Set to 0, AV
f
± 1% Specified Performance
Typically 10 nA, V
I
I
Coding Bit Set to 1
Coding Bit Set to 0
IN
IN
SAMPLE
SOURCE
SINK
= 50 kHz Sine Wave, f
= 400 kHz
= 200 mA
IN
IN
= 200 kSPS
to +REF
= 200 mA, AV
= 2.5 V, f
IN
SCLK
IN
Biased about REF
= 20 MHz, T
= 0 V or V
DD
DD
= 2.7 V to 5.25 V
SCLK
/V
DRIVE
= 20 MHz
DRIVE
A
= T
= 4.75 V to 5.25 V
MIN
IN
to T
with
MAX
REV. 0
, unless