AD7927BRUZ Analog Devices Inc, AD7927BRUZ Datasheet - Page 17

• Manufacturer Part Number: AD7927BRUZ
• Description: IC ADC 12BIT 8CH 200KSPS 20TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7927BRUZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 12
• Sampling Rate (per Second): 200k
• Number Of Converters: 1
• Power Dissipation (max): 7.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 12bit
• Sampling Rate: 200kSPS
• Input Channel Type: Single Ended
• Supply Voltage Range - Analog: 2.7V To 5.25V
• Supply Current: 1.5mA
• Number Of Elements: 1
• Resolution: 12Bit
• Architecture: SAR
• Sample Rate: 200KSPS
• Input Polarity: Unipolar
• Input Type: Voltage
• Rated Input Volt: 2.5/5V
• Differential Input: No
• Power Supply Requirement: Analog and Digital
• Single Supply Voltage (typ): 3/5V
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.25V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 7.5mW
• Differential Linearity Error: -0.9LSB/1.5LSB
• Integral Nonlinearity Error: ±1LSB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: TSSOP
• Input Signal Type: Single-Ended
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7927CBZ - BOARD EVALUATION FOR AD7927
• Lead Free Status / Rohs Status: Compliant

SERIAL INTERFACE
Figure 17 shows the detailed timing diagram for serial interfacing
to the AD7927. The serial clock provides the conversion clock
and also controls the transfer of information to and from the
AD7927 during each conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track and hold into hold mode
and takes the bus out of three-state; the analog input is sampled
at this point. The conversion is also initiated at this point and will
require 16 SCLK cycles to complete. The track and hold will
go back into track on the 14th SCLK falling edge as shown in
Figure 17 at point B, except when the write is to the Shadow
Register, in which case the track and hold will not return to
track until the rising edge of CS, i.e., point C in Figure 18. On
the 16th SCLK falling edge the DOUT line will go back into
three-state. If the rising edge of CS occurs before 16 SCLKs have
elapsed, the conversion will be terminated and the DOUT line
will go back into three-state and the Control Register will not be
updated; otherwise DOUT returns to three-state on the 16th
SCLK falling edge, as shown in Figure 17. Sixteen serial clock
cycles are required to perform the conversion process and to
access data from the AD7927. For the AD7927, the 12 bits of
data are preceded by a leading zero and the three channel address
bits ADD2 to ADD0, identifying which channel the result corre-
sponds to. CS going low provides the leading zero to be read in by
the microcontroller or DSP. The three remaining address bits and
data bits are then clocked out by subsequent SCLK falling edges
beginning with the first address bit ADD2, thus the first falling
clock edge on the serial clock has a leading zero provided and
also clocks out address bit ADD2. The final bit in the data
transfer is valid on the 16th falling edge, having been clocked
out on the previous (15th) falling edge.
REV. 0
DOUT
DOUT
SCLK
SCLK
DIN
DIN
CS
CS
THREE-
STATE
THREE-
STATE
ZERO
ZERO
t
t
WRITE
2
2
V
IN
1
1
t
0
t
3
3
ADD2
ADD2
3 IDENTIFICATION BITS
3 IDENTIFICATION BITS
Figure 18. Writing to Shadow Register Timing Diagram
t
t
9
SEQ
9
V
SEQUENCE 1
IN
1
2
2
ADD1
ADD1
Figure 17. Serial Interface Timing Diagram
DONTC
V
IN
2
3
3
ADD0
ADD0
ADD2
V
IN
3
4
4
DB11
t
t
t
DB11
CONVERT
CONVERT
t
4
4
t
6
ADD1
t
6
V
IN
t
10
4
t
5
5
10
–17–
DB10
DB10
ADD0
V
Writing of information to the Control Register takes place on the
first 12 falling edges of SCLK in a data transfer, assuming the MSB,
i.e., the WRITE bit, has been set to 1. If the Control Register is
programmed to use the Shadow Register, then the writing of
information to the Shadow Register will take place on all 16 SCLK
falling edges in the next serial transfer as shown for example on the
AD7927 in Figure 18. Two sequence options can be programmed
in the Shadow Register. If the user does not want to program a
second sequence, then the eight LSBs should be filled with zeros.
The Shadow Register will be updated upon the rising edge of
CS and the track and hold will begin to track the first channel
selected in the sequence.
The 16-bit word read from the AD7927 will always contain a
leading zero, three channel address bits that the conversion
result corresponds to, followed by the 12-bit conversion result.
Writing Between Conversions
As outlined in the Operating Modes section, not less than 5 ms
should be left between consecutive valid conversions. However,
there is one case where this does not necessarily mean that at least
5 ms should always be left between CS falling edges. Consider the
case when writing to the AD7927 to power it up from shutdown
prior to a valid conversion. The user must write to the part to tell
it to power up before it can convert successfully. Once the serial
write to power up has finished, one may wish to perform the con-
version as soon as possible and not have to wait a further 5 ms
before bringing CS low for the conversion. In this case, as long
as there is a minimum of 5 ms between each valid conversion, then
only the quiet time between the CS rising edge at the end of the
write to power up and the next CS falling edge for a valid con-
version needs to be met. Figure 19 illustrates this point. Note
IN
5
t
7
t
7
13
SEQUENCE 2
13
DB2
DB2
DONTC
B
V
IN
14
t
5
5
14
t
5
DB1
DONTC
DB1
V
IN
15
6
15
t
8
DB0
t
DONTC
DB0
8
V
16
IN
t
11
16
7
THREE-
STATE
THREE-
STATE
t
11
C
t
QUIET
AD7927