AD7194BCPZ Analog Devices Inc, AD7194BCPZ Datasheet - Page 47

• Manufacturer Part Number: AD7194BCPZ
• Description: IC ADC 24BIT SPI 4.8K 32-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD7194BCPZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 24
• Sampling Rate (per Second): 4.8k
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 32-WFQFN, CSP Exposed Pad
• Resolution (bits): 24bit
• Input Channel Type: Pseudo Differential
• Supply Voltage Range - Analogue: 3V To 5.25V
• Supply Voltage Range - Digital: 2.7V To 5.25V
• Supply: RoHS Compliant
• Sampling Rate: 4.8kSPS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AD7194BRUZ; AD7194BRUZ

of 42.10 Hz when the master clock equals 4.92 MHz. The sinc
filter places the first notch at
The postfiltering places notches at f
amount of averaging) and multiples of this frequency; therefore,
when FS[9:0] is set to 6 and the postfilter averaging is 16, a
notch is placed at 800 Hz due to the sinc filter and notches are
placed at 50 Hz and multiples of 50 Hz due to the postfilter. The
notch at 50 Hz is a first-order notch; therefore, the notch is not
wide. This means that the rejection at 50 Hz exactly is good,
assuming a stable 4.92 MHz master clock. However, in a band
of 50 Hz ± 1 Hz, the rejection degrades significantly. The
rejection at 50 Hz ± 0.5 Hz is 40 dB minimum, assuming a
stable clock; therefore, a good master clock source is
recommended when using fast settling mode.
Figure 57 shows the filter response when FS[9:0] is set to 5 and
the postfilter averages by 16. In this case, the output data rate is
equal to 50.53 Hz (4.92 MHz master clock) while the first filter
notch is placed at 60 Hz. The rejection at 60 Hz ± 0.5 Hz is
equal to 40 dB minimum.
f
NOTCH
–100
–120
–100
–120
–110
–110
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
Figure 56. Filter Response for Average + Decimate Filter
Figure 57. Filter Response for Average + Decimate Filter
0
0
= f
CLK
(Sinc
(Sinc
/(1024 × FS[9:0])
30
30
4
4
Filter, FS[9:0] = 6, Average by 16)
Filter, FS[9:0] = 5, Average by 16)
FREQUENCY (Hz)
FREQUENCY (Hz)
60
60
NOTCH
90
90
/Avg (Avg is the
120
120
15
150
0
Rev. 0 | Page 47 of 56
Simultaneous 50 Hz/60 Hz rejection is achieved when FS[9:0] is
set to 30 and the postfilter averages by 16. The output data rate
is equal to 8.4 Hz whereas the rejection at 50 Hz ± 0.5 Hz and
60 Hz ± 0.5 Hz is 44 dB typically.
Simultaneous 50 Hz and 60 Hz rejection is also achieved by
using an FS word of 96 and averaging by 16; this places a notch
at 50 Hz. Setting the REJ60 bit to 1 places a notch at 60 Hz (see
Figure 59). The output data rate is reduced to 2.63 Hz with this
configuration but the rejection is improved to 100 dB typically
at 50 Hz ± 1 Hz and 60 Hz ± 1 Hz.
–100
–120
–110
–100
–110
–120
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
Figure 58. Filter Response for Average + Decimate Filter
Figure 59. Filter Response for Average + Decimate Filter
0
0
(Sinc
(Sinc
30
30
4
4
Filter, FS[9:0] = 30, Average by 16)
Filter, FS[9:0] = 96, Average by 16)
FREQUENCY (Hz)
FREQUENCY (Hz)
60
60
90
90
120
120
AD7194
150
150