AD7194BCPZ Analog Devices Inc, AD7194BCPZ Datasheet - Page 26

IC ADC 24BIT SPI 4.8K 32-LFCSP

AD7194BCPZ

Manufacturer Part Number
AD7194BCPZ
Description
IC ADC 24BIT SPI 4.8K 32-LFCSP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD7194BCPZ

Data Interface
DSP, MICROWIRE™, QSPI™, Serial, SPI™
Number Of Bits
24
Sampling Rate (per Second)
4.8k
Number Of Converters
1
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
32-WFQFN, CSP Exposed Pad
Resolution (bits)
24bit
Input Channel Type
Pseudo Differential
Supply Voltage Range - Analogue
3V To 5.25V
Supply Voltage Range - Digital
2.7V To 5.25V
Supply
RoHS Compliant
Sampling Rate
4.8kSPS
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
AD7194BRUZ
AD7194BRUZ

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD7194BCPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD7194
Channel Selection (Pseudo Bit = 0)
Table 22. Positive Input Selection
Positive Input Enable Bits in
the Configuration Register
CH7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Table 24. Channel Selection (Pseudo Bit = 1)
CH7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Channel Enable Bits in the Configuration Register
CH6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CH6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CH5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CH5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CH4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CH4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Positive
Input Enabled
AIN(+)
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
AIN16
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CH3
CH2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Status
Register Bits
CHD[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
CH1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Rev. 0 | Page 26 of 56
CH0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
AIN16
Positive Input AIN(+)
Table 23. Negative Input Selection
CH3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Negative Input Enable Bits in the
Configuration Register
CH2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Channel Enabled
Negative Input AIN(−)
AINCOM
AINCOM
AINCOM
AINCOM
AINCOM
AINCOM
AINCOM
AINCOM
AINCOM
AINCOM
AINCOM
AINCOM
AINCOM
AINCOM
AINCOM
AINCOM
CH1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CH0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Status Register
Bits CHD[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Negative
Input Enabled
AIN(−)
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
AIN16

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