AD7194BCPZ Analog Devices Inc, AD7194BCPZ Datasheet - Page 41

• Manufacturer Part Number: AD7194BCPZ
• Description: IC ADC 24BIT SPI 4.8K 32-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD7194BCPZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 24
• Sampling Rate (per Second): 4.8k
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 32-WFQFN, CSP Exposed Pad
• Resolution (bits): 24bit
• Input Channel Type: Pseudo Differential
• Supply Voltage Range - Analogue: 3V To 5.25V
• Supply Voltage Range - Digital: 2.7V To 5.25V
• Supply: RoHS Compliant
• Sampling Rate: 4.8kSPS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AD7194BRUZ; AD7194BRUZ

The output data rate is 50 Hz when zero latency is disabled and
12.5 Hz when zero latency is enabled. Figure 34 shows the
frequency response of the sinc
±1 Hz and 60 Hz ± 1 Hz rejection of 82 dB minimum, assuming
a stable 4.92 MHz master clock.
SINC
A sinc
selected using the SINC3 bit in the mode register. The sinc
filter is selected when the SINC3 bit is set to 1.
This filter has good noise performance when operating with
output data rates up to 1 kHz. It has moderate settling time and
moderate 50 Hz/60 Hz (±1 Hz) rejection.
Sinc
The output data rate (the rate at which conversions are available
on a single channel when the ADC is continuously converting)
is equal to
where:
f
f
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
The output data rate can be programmed from 4.7 Hz to
4800 Hz; that is, FS[9:0] can have a value from 1 to 1023.
The settling time is equal to
ADC
CLK
is the master clock (4.92 MHz nominal).
is the output data rate.
3
f
t
ADC
–100
–120
SETTLE
–110
Output Data Rate and Settling Time
3
3
–10
–20
–30
–40
–50
–60
–70
–80
–90
filter can be used instead of the sinc
FILTER (CHOP DISABLED)
0
= f
Figure 34. Sinc
0
CHOP
= 3/f
CLK
/(1024 × FS[9:0])
ADC
Figure 35. Sinc
25
MODULATOR
4
Filter Response (FS[9:0] = 96, REJ60 = 1)
50
FREQUENCY (Hz)
3
Filter (Chop Disabled)
4
ADC
SINC
filter. The filter provides 50 Hz
75
3
/SINC
4
100
4
POST FILTER
filter. The filter is
125
150
3
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The 3 dB frequency is equal to
Table 30 gives some examples of FS settings and the corres-
ponding output data rates and settling times.
Table 30. Examples of Output Data Rates and the
Corresponding Settling Time
FS[9:0]
480
96
80
When a channel change occurs, the modulator and filter reset.
The complete settling time is allowed to generate the first
conversion after the channel change (see Figure 36). Subsequent
conversions on this channel are available at 1/f
When conversions are performed on a single channel and a step
change occurs, the ADC does not detect the change in analog
input. Therefore, it continues to output conversions at the
programmed output data rate. However, it is at least three
conversions later before the output data accurately reflects the
analog input. If the step change occurs while the ADC is
processing a conversion, the ADC takes four conversions after
the step change to generate a fully settled result.
Sinc
Zero latency is enabled by setting the single bit (Bit 11) in the
mode register to 1. With zero latency, the complete settling time
is allowed for each conversion. Therefore, the conversion time
when converting on a single channel or when converting on
several channels is constant. The user does not need to consider
the effects of channel changes on the output data rate.
CONVERSIONS
3
f
ANALOG
3dB
OUTPUT
CHANNEL
Zero Latency
INPUT
= 0.272 × f
ADC
Figure 37. Asynchronous Step Change in Analog Input
Output Data Rate (Hz)
10
50
60
CH A
CHANNEL A
Figure 36. Sinc
ADC
CH A CH A
1/
3
f
ADC
Channel Change
1/
CHANNEL B
f
ADC
Settling Time (ms)
300
60
50
CH B
ADC
CH B
SETTLED
FULLY
.
CH B
AD7194
CH B