MAXQ3180-RAN+ Maxim Integrated Products, MAXQ3180-RAN+ Datasheet - Page 36

• Manufacturer Part Number: MAXQ3180-RAN+
• Description: IC AFE POLYPHASE MULTI 28-TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAXQ3180-RAN+

• Number Of Channels: 8
• Power (watts): 35mW
• Voltage - Supply, Analog: 3.6V
• Voltage - Supply, Digital: 3.6V
• Package / Case: 28-TSSOP
• For Use With: MAXQ3180-KIT - KIT EV REFRNC DSIGN FOR MAXQ3180
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Bits: -

Low-Power, Multifunction, Polyphase AFE
This register selects which phases are included in the CFQ pulse output and also selects which quantity is accumu-
lated to drive the pulse output.
This register designates the width of the CFP pulse, that is, the duration of the period that the CFP pulse is in the
active state. This value is given in ADC frame times (about 320μs). The default value of 0x9C (156 decimal) provides
a pulse width of about 50ms.
36
Bit:
Name:
Reset:
Bit:
Name:
Reset:
Bit:
Name:
Reset:
BIT
7:3
______________________________________________________________________________________
2
1
0
PHASEC
PHASEB
PHASEA
QNSEL
NAME
15
7
7
CFQ Pulse Output Source Select. This five-bit field determines what meter value is accumulated in
each of the phases to produce the CFQ pulse output. All other values are reserved.
00000 = Net real energy
00001 = Absolute real energy
00010 = Net reactive energy
00011 = Absolute reactive energy
00100 = Apparent energy
00110 = I
00111 = V
01000 = Real energy delivered to load
01001 = Real energy delivered to line
01010 = Reactive energy, quadrant I
01011 = Reactive energy, quadrant II
01100 = Reactive energy, quadrant III
01101 = Reactive energy, quadrant IV
CFQ Phase C Inclusion. When this bit is set, phase C is included in CFQ pulse generation.
CFQ Phase B Inclusion. When this bit is set, phase B is included in CFQ pulse generation.
CFQ Phase A Inclusion. When this bit is set, phase A is included in CFQ pulse generation.
14
RMS
6
6
RMS
QNSEL
0x0
13
5
5
Pulse Configuration—CFQ Output (PLSCFG2) (0x01F)
CFP Pulse-Width High Byte
CFP Pulse-Width Low Byte
12
4
4
0x9C
0x00
FUNCTION
CFP Pulse Width (PLS1_WD) (0x020)
11
3
3
PHASEC
10
2
0
2
PHASEB
1
0
9
1
PHASEA
0
0
8
0