MAXQ3181-RAN+ Maxim Integrated Products, MAXQ3181-RAN+ Datasheet - Page 33

• Manufacturer Part Number: MAXQ3181-RAN+
• Description: IC AFE POLYPHASE LO-PWR 28-TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAXQ3181-RAN+

• Number Of Channels: 8
• Power (watts): 35mW
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 3.3V
• Package / Case: 28-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Bits: -

This register selects which phases are included in the CFP pulse output and also selects which quantity is accumu-
lated to drive the pulse output.
This register designates the width of the CFP pulse, that is, the duration of the period that the CFP pulse is in the
active state. This value is given in ADC frame times (about 320μs). The default value of 0x9C (156 decimal) provides
a pulse width of about 50ms.
Bit:
Name:
Reset:
Bit:
Name:
Reset:
Bit:
Name:
Reset:
BIT
7:3
2
1
0
PHASEC
PHASEB
PHASEA
QNSEL
NAME
Low-Power, Active Energy, Polyphase AFE
______________________________________________________________________________________
15
7
7
CFP Pulse Output Source Select. This five-bit field determines what meter value will be accumulated in
each of the phases to produce the CFP pulse output. All other values are reserved.
00000 = Net real energy
00001 = Absolute real energy
00100 = Apparent energy
00110 = I
00111 = V
01000 = Real energy delivered to load
01001 = Real energy delivered to line
CFP Phase C Inclusion. When this bit is set, phase C is included in CFP pulse generation.
CFP Phase B Inclusion. When this bit is set, phase B is included in CFP pulse generation.
CFP Phase A Inclusion. When this bit is set, phase A is included in CFP pulse generation.
14
RMS
6
6
RMS
QNSEL
0x0
13
5
5
Pulse Configuration—CFP Output (PLSCFG1) (0x01E)
CFP Pulse-Width High Byte
CFP Pulse-Width Low Byte
12
4
4
0x9C
0x00
FUNCTION
CFP Pulse Width (PLS1_WD) (0x020)
11
3
3
Meter Pulse Configuration
PHASEC
10
2
2
0
PHASEB
1
0
9
1
PHASEA
8
0
0
0
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