IDT82V3380PFG IDT, Integrated Device Technology Inc, IDT82V3380PFG Datasheet - Page 7

• Manufacturer Part Number: IDT82V3380PFG
• Description: IC PLL WAN SYNC ETH 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3380PFG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3380PFG

IDT82V3380
SYNCHRONOUS ETHERNET WAN PLL
Table 49: AMI Input / Output Port Electrical Characteristics ...................................................................................................................................... 155
Table 50: CMOS Input Port Electrical Characteristics ............................................................................................................................................... 156
Table 51: CMOS Input Port with Internal Pull-Up Resistor Electrical Characteristics ................................................................................................ 156
Table 52: CMOS Input Port with Internal Pull-Down Resistor Electrical Characteristics ........................................................................................... 156
Table 53: CMOS Output Port Electrical Characteristics ............................................................................................................................................ 156
Table 54: PECL Input / Output Port Electrical Characteristics ................................................................................................................................... 158
Table 55: LVDS Input / Output Port Electrical Characteristics ................................................................................................................................... 159
Table 56: Output Clock Jitter Generation .................................................................................................................................................................. 161
Table 57: Output Clock Phase Noise ......................................................................................................................................................................... 162
Table 58: Input Jitter Tolerance (155.52 MHz) .......................................................................................................................................................... 162
Table 59: Input Jitter Tolerance (1.544 MHz) ............................................................................................................................................................ 162
Table 60: Input Jitter Tolerance (2.048 MHz) ............................................................................................................................................................ 162
Table 61: Input Jitter Tolerance (8 kHz) .................................................................................................................................................................... 162
Table 62: T0 DPLL Jitter Transfer & Damping Factor ............................................................................................................................................... 163
Table 63: T4 DPLL Jitter Transfer & Damping Factor ............................................................................................................................................... 163
Table 64: Input/Output Clock Timing 3 ...................................................................................................................................................................... 165
Table 65: Output Clock Timing .................................................................................................................................................................................. 167
List of Tables
7
May 19, 2009