IDT82V3380PFG IDT, Integrated Device Technology Inc, IDT82V3380PFG Datasheet

IDT82V3380PFG

Manufacturer Part Number

IDT82V3380PFG

Description

IC PLL WAN SYNC ETH 100-TQFP

Manufacturer

IDT, Integrated Device Technology Inc

Type

PLL Clock Generatorr

Datasheets

1.IDT82V3380PFG8.pdf (175 pages)

2.IDT82V3380PFG8.pdf (1 pages)

Specifications of IDT82V3380PFG

Input

CMOS, LVDS, PECL, TTL

Output

CMOS, LVDS, PECL, TTL

Frequency - Max

622.08MHz

Voltage - Supply

3 V ~ 3.6 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

100-TQFP, 100-VQFP

Frequency-max

622.08MHz

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

82V3380PFG

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

IDT82V3380PFG

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

Company:

BOSTOCK HK LIMITED

Part Number:

IDT82V3380PFG8

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

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 2009 Integrated Device Technology, Inc.

IDT82V3380 Device Errata

Notes

Supplemental Information

of the IN14 if this input reference selector is set for Force Select to IN14 and MFRSYNC_2K of the master

and slave devices synchronization to each other in pulse mode.

Description

Force Select to IN14.

highest priority valid clock [or Register 2Ch, Bit 7-4 IN14_SEL_PRIORITY[3:0]= ‘0001’] among the valid

input references and the switch mode is set to ‘revertive mode’ [or Register 09h, bit 0 = ‘1’], then the

IDT82V3380 will always lock to IN14. If there is only one valid input reference at IN14, then other input

references can be changed to in-valid by setting the ‘remote-valid’ bit to ‘1’ [or Register 4Ch and Register

4Dh bits set to all ‘1’ except Register 4D bit 5 = ‘0’].

Description

slave EX_SYNC1 must be connected to the master MFRSYNC_2K. If MFRSYNC_2K is placed in pulsed

mode, then the master MFRSYNC_2K pulse and slave MFRSYNC_2K will not synchronize to each other

after the slave is reset or after the slave is reset and the slave registers are reloaded.

'0'] in order for the slave MFRSYNC_2K to sync to the master MFRSYNC_2K. The FRSYNC_8K will

synchronize in both clock mode and pulse mode.

This errata supplements the datasheet. It provides information regarding an IDT82V3380 locking status

The IDT82V3380 T0 and T4 PLL will always stay in holdover mode if the reference selector is set for

Work-Around: The software must place IDT82V3380 IN14 in Auto Select mode and set IN14 at the

This known discrepancy is fixed in the new silicon IDT82V3380A revision.

In master-slave configurations where both MFRSYNC_2K and FRSYNC_8K must be synchronized, the

Work-Around: The IDT82V3380 master MFRSYNC_2K must be in clock mode [or Register 74h bit 0 =

This known discrepancy is fixed in the new silicon IDT82V3380A revision.

IDT82V3380 Device Errata

July 28, 2009

DSC-7240/-

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