MC88915TEI133 IDT, Integrated Device Technology Inc, MC88915TEI133 Datasheet - Page 13

• Manufacturer Part Number: MC88915TEI133
• Description: IC PLL CLOCK DRIVER 28-PLCC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Driverr

Specifications of MC88915TEI133

• Pll: Yes with Bypass
• Input: TTL
• Output: CMOS, TTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: No/No
• Frequency - Max: 133MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Frequency-max: 133MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ / ICS™ CMOS PLL CLOCK DRIVERS
MC88915T
LOW SKEW CMOS PLL CLOCK DRIVERS, 3-STATE
5.
Table 23. Relative Positions of Outputs Q/2, Q0–Q4,
2X_Q Within the 500 ps t
6.
EXTERNAL LOOP FILTER
The t
outputs Q/2, Q0, Q1, Q2, Q3, and Q4 will always fall
within a 500 ps window within one part. However, if the
relative position of each output within this window is not
specified, the 500 ps window must be added to each
side of the t
part-to-part skew. For this reason, the absolute
distribution of these outputs are provided in
When taking the skew data, Q0 was used as a
reference, so all measurements are relative to this
output. The information in
measurements taken from the 14 process lots described
in Note 1, over the temperature and voltage range.
Calculation of Total Output-to-Skew Between
Multiple Parts (Part-to-Part Skew)
By combining the t
Note 5, the worst case output-to-output skew between
multiple 88915s connected in parallel can be calculated.
This calculation assumes all parts have a common
FEEDBACK OUTPUT
Output
2X_Q
SYNC INPUT
With the 1.0 MΩ resistor tied in this fashion, the t
specification measured at the input pins is:
Q/2
Q0
Q1
Q2
Q3
Q4
SKEWr
t
PD
specification guarantees the rising edges of
PD
= 2.25 ns ± 1.0 ns
specification limits to calculate the total
PD
0.1 µF
2.25 ns OFFSET
specification and the information in
330 Ω
SKEWr
– (ps)
Which is Present When a 1 mΩ Resistor is Tied to V
–274
–633
–72
–44
–40
–16
Figure 4. Depiction of the Fixed SYNC to Feedback Offset (t
0
RC1
Table 23
Spec Window
R2
C1
is derived from
ANALOG GND
3.0 V
1.5 MΩ
1 MΩ or
REFERENCE
RESISTOR
+ (ps)
Table
276
255
–34
250
–35
40
0
PD
5.0 V
23.
13
7.
SYNC input clock with equal delay of input signal to each
part. This skew value is valid at the 88915 output pins
only (equally loaded), it does not include PCB trace de-
lays due to varying loads.
With a 1.0 MΩ resistor tied to analog V
Note 4, the t
output (connected to the FEEDBACK pin) are –1.05 ns
and –0.5 ns. To calculate the skew of any given output
between two or more parts, the absolute value of the dis-
tribution of the output given in
ed and added to the lower and upper t
respectively. For output Q2, [276 – (–44)] = 320 ps is the
absolute value of the distribution. Therefore, [–1.05 ns –
0.32 ns] = –1.37 ns is the lower t
0.32 ns] = –0.18 ns is the upper limit. Therefore, the
worst case skew of output Q2 between any number of
parts is |(–1.37) – (–0.18)| = 1.19 ns. Q2 has the worst
case skew distribution of any output, so 1.2 ns is the ab-
solute worst case output-to-output skew between multi-
ple parts.
Note 4 explains the t
is guaranteed for the configuration of the Q/2 output
connected to the FEEDBACK pin and the SYNC input
running at 10 MHz. The fixed offset (t
above has some dependence on the input frequency
and at what frequency the VCO is running. The graphs
of
The data presented in
senting process extremes, and the measurements were
also taken at the voltage extremes (V
4.75 V). Therefore, the data in
resentation of the variation of t
FEEDBACK OUTPUT
Figure 5
SYNC INPUT
With the 1.0 MΩ resistor tied in this fashion, the t
specification measured at the input pins is:
demonstrate this dependence.
REFERENCE
PD
CC
t
PD
RESISTOR
spec. limits between SYNC and the Q/2
1 MΩ or
or Ground
= –0.775 ns ± 0.275 ns
1.5 MΩ
ANALOG V
PD
PD
Figure 5
specification was measured and
)
0.1 µF
CC
330 Ω
Table 23
PD
Figure 5
is from devices repre-
–0.775 ns OFFSET
PD
.
MC88915TREV 7 JULY 10, 2007
RC1
limit, and [–0.5 ns +
R2
PD
CC
C1
ANALOG GND
PD
must be subtract-
CC
is a realistic rep-
) as described
= 5.25 V and
spec limits
as shown in
5.0 V
3.0 V
PD