MC88915TEI133 IDT, Integrated Device Technology Inc, MC88915TEI133 Datasheet - Page 11

• Manufacturer Part Number: MC88915TEI133
• Description: IC PLL CLOCK DRIVER 28-PLCC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Driverr

Specifications of MC88915TEI133

• Pll: Yes with Bypass
• Input: TTL
• Output: CMOS, TTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: No/No
• Frequency - Max: 133MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Frequency-max: 133MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ / ICS™ CMOS PLL CLOCK DRIVERS
Table 21. AC Characteristics (T
MC88915T
LOW SKEW CMOS PLL CLOCK DRIVERS, 3-STATE
t
Outputs
t
2X_Q Output
t
(Q0–Q4, Q5, Q/2)
t
(2X_Q Output)
t
SYNC Feedback
t
(2x_Q Output)
t
(Rising)
t
(Falling)
t
t
t
t
RISE/FALL
RISE/FALL
PULSEWIDTH
PULSEWIDTH
PD
CYCLE
SKEWr
SKEWf
SKEWall
LOCK
PZL
PHZ
1. T
2. The T
3. Under equally loaded conditions and at a fixed temperature and voltage.
4. With V
(1)
with C1 = 0.01 µF.
, t
Symbol
CYCLE
(4)
PLZ
(3)
(3)
(4)
(3)
PD
CC
in this spec is 1/Frequency at which the particular output is running.
specification’s min/max values may shift closer to zero if a larger pullup resistor is used.
fully powered on, and an output properly connected to the FEEDBACK pin. t
Rise/Fall Time, All Outputs
(Between 0.2 V
Rise/Fall Time
Output Pulse Width: Q0, Q1, Q2, Q4, Q4,
Q5, Q/2 @ V
Output Pulse Width: 80 MHz
2X_Q @ 1.5 V100 MHz
133 MHz
160 MHz
SYNC Input to Feedback Delay
(Measured at SYNC0 or 1
and FEEDBACK Input Pins)
133 MHz
160 MHz
Cycle-to-Cycle Variation133 MHz
160 MHz
Output-to-Output Skew Between Outputs Q0–Q4,
Q/2 (Rising Edges Only)
Output-to-Output Skew Between Outputs Q0–Q4
(Falling Edges Only)
Output-to-Output Skew 2X_Q, Q/2, Q0–Q4 Rising,
Q5 Falling
Time Required to Acquire Phase-Lock from Time
SYNC Input Signal is Received
Output Enable Time OE/RST to 2X_Q, Q0–Q4,
Q5, and Q/2
Output Disable Time OE/RST to 2X_Q, Q0–Q4,
Q5, and Q/2
CC
CC
/2
A
and 0.8 V
Parameter
= 0°C to +70°C, V
CC
)
MC88915TFN160 (Continued)
CC
= 5.0 V ± 5%, Load = 50 Ω Terminated to V
0.5 t
0.5 t
0.5 t
0.5 t
t
t
CYCLE
CYCLE
(With 1 MΩ from RC1 to An V
11
CYCLE
CYCLE
CYCLE
CYCLE
–1.05
TBD
–0.9
Min
1.0
0.5
1.0
3.0
3.0
—
—
—
– 300 ps
– 300 ps
– 0.5
– 0.7
– 0.5
– 0.5
(2)
LOCK
0.5 t
0.5 t
0.5 t
0.5 t
t
t
CYCLE
CYCLE
CYCLE
maximum is with C1 = 0.1 µF, t
CYCLE
CYCLE
CYCLE
–0.25
–0.10
TBD
Max
500
500
750
2.5
1.6
10
14
14
+ 300 ps
+ 300 ps
+ 0.5
+ 0.7
+ 0.5
+ 0.5
CC
)
(2)
Unit
CC
ms
ns
ns
ns
ns
ns
ps
ps
ps
ns
ns
/2)
MC88915TREV 7 JULY 10, 2007
Into a 50 Ω Load
Terminated to V
t
t
Into a 50 Ω Load
Terminated to V
See Note
Figure 4
Explanation
All Outputs into a
Matched 50 Ω Load
Terminated to V
All Outputs into a
Matched 50 Ω Load
Terminated to V
All Outputs into a
Matched 50 Ω Load
Terminated to V
Also Time to LOCK
Indicator High
Measured with the
PLL_EN Pin Low
Measured with the
PLL_EN Pin Low
RISE
FALL
: 0.8 V – 2.0 V
: 2.0 V – 0.8 V
LOCK
Condition
for Detailed
(2)
minimum is
and
CC
CC
CC
CC
CC
/2
/2
/2
/2
/2