MPC9350AC IDT, Integrated Device Technology Inc, MPC9350AC Datasheet - Page 8

• Manufacturer Part Number: MPC9350AC
• Description: IC PLL CLOCK DRIVER LV 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC9350AC

• Pll: Yes with Bypass
• Input: LVCMOS, Crystal
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:9
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ Low Voltage PLL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9350
Low Voltage PLL Clock Driver
8
output-to-output skew of the MPC9350. The output waveform
in
by the impedance mismatch seen looking into the driver. The
parallel combination of the 36 Ω series resistor plus the
output impedance does not match the parallel combination of
the line impedances. The voltage wave launched down the
two lines will equal:
unity reflection coefficient, to 2.5 V. It will then increment
toward the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
MPC9350
Figure 5
At the load end the voltage will double, due to the near
3.0
2.5
2.0
1.5
1.0
0.5
0
Figure 5. Single versus Dual Waveforms
shows a step in the waveform. This step is caused
t
D
2
V
Z
R
R
V
= 3.8956
OutA
0
In
L
L
S
0
= V
= 50 Ω || 50 Ω
= 36 Ω || 36 Ω
= 17 Ω
= 3.0 (25 ÷ (18+17+25))
= 1.25 V
4
S
Figure 7. TCLK MPC9350 AC Test Reference for V
(Z
0
÷ (R
6
Generator
Z = 50Ω
Time (ns)
Pulse
t
D
S
+R
= 3.9386
OutB
8
0
+Z
0
))
10
12
Z
O
= 50Ω
R
T
= 50Ω
14
V
TT
8
MPC9350 DUT
cause any false clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines, the
situation in
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance, the line
impedance is perfectly matched.
Since this step is well above the threshold region, it will not
Figure 6. Optimized Dual Line Termination
CC
MPC9350
Figure 6
Output
Buffer
14Ω
= 3.3 V and V
14Ω + 22Ω || 22Ω = 50Ω || 50Ω
Z
O
should be used. In this case the series
= 50Ω
25Ω = 25Ω
R
R
S
S
CC
= 22Ω
= 22Ω
Advanced Clock Drivers Devices
R
T
= 2.5 V
= 50Ω
Freescale Semiconductor
V
Z
Z
TT
O
O
= 50Ω
= 50Ω
NETCOM
MPC9350