MPC9350AC IDT, Integrated Device Technology Inc, MPC9350AC Datasheet - Page 6

• Manufacturer Part Number: MPC9350AC
• Description: IC PLL CLOCK DRIVER LV 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC9350AC

• Pll: Yes with Bypass
• Input: LVCMOS, Crystal
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:9
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ Low Voltage PLL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9350
Low Voltage PLL Clock Driver
6
Programming the MPC9350
several divider modes. In addition, the internal feedback of
the device allows for flexibility in establishing two input to
output frequency relationships. The output division settings
establish the output frequency relationship. The output
divider of the four output groups allows the user to configure
the outputs into 1:1, 2:1, 4:1 and 4:2:1 frequency ratios. The
use of even dividers ensures that the output duty cycle is
always 50%.
Table 7. Output Frequency Relationship
Table 8. Output Frequency Relationship
MPC9350
1. Output frequency relationship with respect to input reference frequency CLK. Consult the MPC9351 data sheet for more input to output
1. Output frequency relationship with respect to input reference frequency CLK. Consult the MPC9351 data sheet for more input to output
The MPC9350 clock driver outputs can be configured into
relationships in external feedback mode.
relationships in external feedback mode.
FSELA
FSELA
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Table 7
FSELB
FSELB
and
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Table 8
Inputs
Inputs
illustrate the various output
FSELC
FSELC
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
(1)
(1)
FBSEL = 0, (VC0 = 32 * CLK)
FBSEL = 1, (VC0 = 16 * CLK)
APPLICATIONS INFORMATION
FSELD
FSELD
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
6
configurations. The tables describe the outputs using the
input clock frequency CLK as a reference.
given the frequency of the outputs desired. The feedback
frequency should be used to situate the VCO into a frequency
range in which the PLL will be stable. The design of the PLL
supports output frequencies from 25 MHz to 200 MHz while
the VCO frequency range is specified from 200 MHz to
400 MHz and should not be exceeded for stable operation.
16 * CLK
16 * CLK
16 * CLK
16 * CLK
16 * CLK
16 * CLK
16 * CLK
16 * CLK
8 * CLK
8 * CLK
8 * CLK
8 * CLK
8 * CLK
8 * CLK
8 * CLK
8 * CLK
8 * CLK
8 * CLK
8 * CLK
8 * CLK
8 * CLK
8 * CLK
8 * CLK
8 * CLK
4 * CLK
4 * CLK
4 * CLK
4 * CLK
4 * CLK
4 * CLK
4 * CLK
4 * CLK
In addition, it must be ensured that the VCO will be stable
QA
QA
8 * CLK
8 * CLK
8 * CLK
8 * CLK
4 * CLK
4 * CLK
4 * CLK
4 * CLK
8 * CLK
8 * CLK
8 * CLK
8 * CLK
4 * CLK
4 * CLK
4 * CLK
4 * CLK
4 * CLK
4 * CLK
4 * CLK
4 * CLK
2 * CLK
2 * CLK
2 * CLK
2 * CLK
4 * CLK
4 * CLK
4 * CLK
4 * CLK
2 * CLK
2 * CLK
2 * CLK
2 * CLK
QB
QB
Outputs
Outputs
Advanced Clock Drivers Devices
QC0, QC1
QC0, QC1
8 * CLK
8 * CLK
4 * CLK
4 * CLK
8 * CLK
8 * CLK
4 * CLK
4 * CLK
8 * CLK
8 * CLK
4 * CLK
4 * CLK
8 * CLK
8 * CLK
4 * CLK
4 * CLK
4 * CLK
4 * CLK
2 * CLK
2 * CLK
4 * CLK
4 * CLK
2 * CLK
2 * CLK
4 * CLK
4 * CLK
2 * CLK
2 * CLK
4 * CLK
4 * CLK
2 * CLK
2 * CLK
Freescale Semiconductor
QD0–QD4
QD0–QD4
8 * CLK
4 * CLK
8 * CLK
4 * CLK
8 * CLK
4 * CLK
8 * CLK
4 * CLK
8 * CLK
4 * CLK
8 * CLK
4 * CLK
8 * CLK
4 * CLK
8 * CLK
4 * CLK
4 * CLK
2 * CLK
4 * CLK
2 * CLK
4 * CLK
2 * CLK
4 * CLK
2 * CLK
4 * CLK
2 * CLK
4 * CLK
2 * CLK
4 * CLK
2 * CLK
4 * CLK
2 * CLK
NETCOM
MPC9350