MPC9350AC IDT, Integrated Device Technology Inc, MPC9350AC Datasheet

MPC9350AC

Manufacturer Part Number

MPC9350AC

Description

IC PLL CLOCK DRIVER LV 32-LQFP

Manufacturer

IDT, Integrated Device Technology Inc

Type

PLL Clock Generatorr

Datasheet

1.MPC9350ACR2.pdf (11 pages)

Specifications of MPC9350AC

Pll

Yes with Bypass

Input

LVCMOS, Crystal

Output

LVCMOS

Number Of Circuits

Ratio - Input:output

2:9

Differential - Input:output

No/No

Frequency - Max

200MHz

Divider/multiplier

Yes/No

Voltage - Supply

2.375 V ~ 3.465 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

32-LQFP

Frequency-max

200MHz

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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IDT™ Low Voltage PLL Clock Driver

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

Low Voltage PLL Clock Driver

Freescale Semiconductor

Technical Data

Low Voltage PLL Clock Driver

targeted for high performance clock distribution systems. With output

frequencies of up to 200 MHz and maximum output skews of 150 ps, the

MPC9350 is ideal for the most demanding clock tree designs. The device offers

9 low skew clock outputs, with each one configurable to support the clocking

needs of the various high-performance microprocessors, including the

PowerQUICC II integrated communication microprocessor. The extended

temperature range of the MPC9350 supports telecommunication and networking

requirements. The device employs a fully differential PLL design to minimize

cycle-to-cycle and long-term jitter.

Features

•

Functional Description

clock signal. The internal PLL allows the MPC9350 to operate in frequency locked condition and to multiply the input reference

clock. The reference clock frequency and the divider in the internal feedback path determine the VCO frequency. Two selectable

PLL feedback frequency ratios are available on the MPC9350 to provide input frequency range flexibility. The FBSEL pin selects

between divide-by-16 or divide-by-32 of the VCO frequency for PLL feedback. This feedback divider must be selected to match

the VCO frequency range. With the available feedback output dividers, the internal VCO of the MPC9350 is running at either 16x

or 32x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs is either one half, one fourth or one

eighth of the selected VCO frequency and can be configured for each output bank using the FSELA, FSELB, FSELC and FSELD

pins, respectively. The available output to input frequency ratios are 16:1, 8:1, 4:1 and 2:1. The REF_SEL pin selects the crystal

oscillator input or the LVCMOS compatible reference input (TCLK). TCLK also provides an external test clock in static test mode

when the PLL enable pin (PLL_EN) is pulled to logic low state. In test mode, the selected input reference clock is routed directly

to the output dividers without using the PLL. The test mode is intended for system diagnostics, test and debug purposes. This

test mode is fully static and the minimum clock frequency specification does not apply. The outputs can be disabled by

deasserting the OE pin (logic high state). In PLL mode, deasserting OE maintains PLL lock due to the internal feedback path.

The MPC9350 is fully 2.5 V and 3.3 V compatible and requires no external loop filter components. The on-chip crystal oscillator

requires no external components beyond a series resonant crystal. All inputs except the crystal oscillator interface accept

LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission

lines. For series terminated transmission lines, each of the MPC9350 outputs can drive one or two traces giving the device an

effective fanout of 1:18. The device is packaged in a 7x7 mm

The MPC9350 is a 2.5 V and 3.3 V compatible, PLL-based clock generator

The MPC9350 generates high frequency clock signals and provides nine exact frequency-multiplied copies of the reference

9 output LVCMOS PLL clock generator

25 – 200 MHz output frequency range

2.5 V and 3.3 V compatible

Compatible to various microprocessors such as PowerQuicc II

Supports networking, telecommunications and computer applications

Fully integrated PLL

Configurable outputs: divide-by-2, 4 and 8 of VCO frequency

Selectable output to input frequency ratio of 8:1, 4:1, 2:1 or 1:1

Oscillator or crystal reference inputs

Internal PLL feedback

Output disable

PLL enable/disable

Low skew characteristics: maximum 150 ps output-to-output

32-lead LQFP package

32-lead Pb-free Package Available

Temperature range –40°C to +85°C

32-lead LQFP package.

32-LEAD LQFP PACKAGE

CLOCK GENERATOR

3.3 V AND 2.5 V PLL

Pb-FREE PACKAGE

LOW VOLTAGE

CASE 873A-03

FA SUFFIX

AC SUFFIX

DATA SHEET

Rev 6, 4/2005

MPC9350

Related parts for MPC9350AC

MPC9350AC Summary of contents

Page 1

Freescale Semiconductor Technical Data Low Voltage PLL Clock Driver Low Voltage PLL Clock Driver The MPC9350 is a 2.5 V and 3.3 V compatible, PLL-based clock generator targeted for high performance clock distribution systems. With output frequencies ...

Page 2

MPC9350 Low Voltage PLL Clock Driver XTAL1 XTAL2 (Pulldown) TCLK (Pulldown) REF_SEL (Pulldown) FBSEL (Pullup) PLL_EN (Pulldown) FSELA (Pulldown) FSELB (Pulldown) FSELC (Pulldown) FSELD (Pulldown TCLK PLL_EN REF_SEL MPC9350 IDT™ Low Voltage PLL Clock Driver Freescale Timing Solutions ...

Page 3

MPC9350 Low Voltage PLL Clock Driver Table 1. Pin Description Number Name XTAL1, XTAL2 Input TCLK Input FBSEL Input REF_SEL Input FSELA Input FSELB Input FSELC Input FSELD Input OE Input QA Output QB Output QC0, QC1 Output QD0 – ...

Page 4

MPC9350 Low Voltage PLL Clock Driver Table 4. DC Characteristics (V CC Symbol Characteristics V Input high voltage IH V Input low voltage IL V Output High Voltage OH V Output Low Voltage OL I Input Current IN Z Output ...

Page 5

MPC9350 Low Voltage PLL Clock Driver Table 6. DC Characteristics (V CC Symbol Characteristics V Input high voltage IH V Input low voltage IL V Output High Voltage OH V Output Low Voltage OL Z Output impedance OUT I Input ...

Page 6

MPC9350 Low Voltage PLL Clock Driver Programming the MPC9350 The MPC9350 clock driver outputs can be configured into several divider modes. In addition, the internal feedback of the device allows for flexibility in establishing two input to output frequency relationships. ...

Page 7

MPC9350 Low Voltage PLL Clock Driver Power Supply Filtering The MPC9350 is a mixed analog/digital product and as such, it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to ...

Page 8

MPC9350 Low Voltage PLL Clock Driver output-to-output skew of the MPC9350. The output waveform in Figure 5 shows a step in the waveform. This step is caused by the impedance mismatch seen looking into the driver. The parallel combination of ...

Page 9

MPC9350 Low Voltage PLL Clock Driver t The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device. Figure 8. Output-to-Output Skew N+1 The variation ...

Page 10

MPC9350 Low Voltage PLL Clock Driver D1/2 PIN 1 INDEX E1 D/2 4X 0. 28X SEATING PLANE C DETAIL AD 8X (θ1˚ (S) A1 (L1) ...

Page 11

MPC92459 MPC9350 PART NUMBERS 900 MHz Low Voltage LVDS Clock Synthesizer Low Voltage PLL Clock Driver INSERT PRODUCT NAME AND DOCUMENT TITLE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters ...

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