AD9571ACPZLVD Analog Devices Inc, AD9571ACPZLVD Datasheet - Page 4

• Manufacturer Part Number: AD9571ACPZLVD
• Description: IC PLL CLOCK GEN 25MHZ 40LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distribution, Multiplexerr

Specifications of AD9571ACPZLVD

• Pll: Yes
• Input: Crystal
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:10
• Differential - Input:output: No/Yes
• Frequency - Max: 156.25MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.97 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-LFCSP
• Frequency-max: 156.25MHz
• Clock Ic Type: Clock Generator
• Frequency: 25MHz
• No. Of Outputs: 10
• No. Of Multipliers / Dividers: 1
• Supply Voltage Range: 3V To 3.6V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 40
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9571
Parameter
1
LVDS CLOCK OUTPUT JITTER
Typical (typ) is given for V
Table 2.
Jitter Integration
Bandwidth (Typ)
12 kHz to 20 MHz
1.875 MHz to 20 MHz
200 kHz to 10 MHz
1
When the 33.33 MHz, 100 MHz, and 125 MHz clocks are enabled simultaneously, a worst-case −50 dBc spurious content may be presented on Pin 21 and Pin 22 only.
The typical 125 MHz rms jitter data collected from the differential pair of Pin 21 and Pin 22, unless otherwise noted.
PLL Noise (100 MHz LVPECL Output)
Phase Noise (33.33 MHz CMOS Output)
Phase Noise (25 MHz CMOS Output)
Spurious Content
PLL Figures of Merit
PLL Noise (125 MHz LVPECL Output)
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
@ 10 MHz
@ 30 MHz
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
@ 10 MHz
@ 30 MHz
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
@ 5 MHz
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
@ 5 MHz
1
S
100 MHz
0.50
0.30
= 3.3 V, T
A
= 25°C, unless otherwise noted.
Min
125 MHz
33.33 MHz = Off/On
0.41/0.77
0.24/0.66
1
,
Typ
−121
−127
−128
−148
−152
−153
−115
−121
−128
−148
−150
−150
−131
−138
−139
−151
−152
−133
−143
−147
−148
−148
−70
−217.5
Rev. 0 | Page 4 of 20
Max
156.25 MHz
0.41
0.17
Unit
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
dBc/Hz
Unit
ps rms
ps rms
ps rms
Test Conditions/Comments
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
Dominant amplitude with all outputs active
Test Conditions/Comments
LVDS output frequency combinations
are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×
125 MHz, 1 × 33.33 MHz
LVDS output frequency combinations
are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×
125 MHz, 1 × 33.33 MHz
LVDS output frequency combinations
are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×
125 MHz, 1 × 33.33 MHz