AD9571ACPZLVD Analog Devices Inc, AD9571ACPZLVD Datasheet

IC PLL CLOCK GEN 25MHZ 40LFCSP

AD9571ACPZLVD

Manufacturer Part Number
AD9571ACPZLVD
Description
IC PLL CLOCK GEN 25MHZ 40LFCSP
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distribution, Multiplexerr
Datasheet

Specifications of AD9571ACPZLVD

Pll
Yes
Input
Crystal
Output
CMOS, LVDS, LVPECL
Number Of Circuits
1
Ratio - Input:output
1:10
Differential - Input:output
No/Yes
Frequency - Max
156.25MHz
Divider/multiplier
Yes/No
Voltage - Supply
2.97 V ~ 3.63 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
40-LFCSP
Frequency-max
156.25MHz
Clock Ic Type
Clock Generator
Frequency
25MHz
No. Of Outputs
10
No. Of Multipliers / Dividers
1
Supply Voltage Range
3V To 3.6V
Digital Ic Case Style
LFCSP
No. Of Pins
40
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9571ACPZLVD
Manufacturer:
AD
Quantity:
490
FEATURES
Fully integrated VCO/PLL core
Preset divide ratios for 156.25 MHz, 33.33 MHz,100 MHz, and
Choice of LVPECL or LVDS output format
Integrated loop filter
6 copies of reference clock output
Rates configured via strapping pins
Space saving 6 mm × 6 mm 40-lead LFCSP
0.48 W power dissipation (LVDS operation)
0.69 W power dissipation (LVPECL operation)
3.3 V operation
APPLICATIONS
Ethernet line cards, switches, and routers
SCSI, SATA, and PCI-express
PCI support included
Low jitter, low phase noise clock generation
GENERAL DESCRIPTION
The AD9571 provides a multioutput clock generator function
comprising a dedicated PLL core that is optimized for Ethernet
line card applications. The integer-N PLL design is based on the
Analog Devices, Inc., proven portfolio of high performance, low
jitter frequency synthesizers to maximize network performance.
Other applications with demanding phase noise and jitter
requirements also benefit from this part.
The PLL section consists of a low noise phase frequency
detector (PFD), a precision charge pump (CP), a low phase
noise voltage controlled oscillator (VCO), and a preprogrammed
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
0.17 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz
0.41 ps rms jitter from 12 kHz to 20 MHz at 125 MHz
Input crystal or clock frequency of 25 MHz
125 MHz
2 × OCTAL
GbE PHY
2 × OCTAL
GbE PHY
Ethernet Clock Generator, 10 Clock Outputs
48 + 2 SWITCH/MAC
XAUI
OPTIONAL
CX-4 PHY
2 × OCTAL
GbE PHY
Figure 2. Typical Application
2 × OCTAL
ISLAND
GbE PHY
CPU
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
feedback divider and output divider. By connecting an external
crystal or reference clock to the REFCLK pin, frequencies up to
156.25 MHz can be locked to the input reference.
Each output divider and feedback divider ratio is prepro-
grammed for the required output rates. No external loop filter
components are required, thus conserving valuable design time
and board space.
The AD9571 is available in a 40-lead 6 mm × 6 mm lead frame
chip scale package and can be operated from a single 3.3 V
supply. The operating temperature range is −40°C to +85°C.
REFCLK
6 × 25MHz
2 × 125MHz
1 × 156.25MHz
1 × 33.33MHz
FUNCTIONAL BLOCK DIAGRAM
XTAL
AD9571
OSC
AD9571
REFSEL
3RD-ORDER
©2009 Analog Devices, Inc. All rights reserved.
PFD/CP
VCO
LPF
Figure 1.
FREQSEL
LVPECL OR
CMOS
LVDS
CMOS
AD9571
www.analog.com
6 × 25MHz
1 × 156.25MHz
2 × 100MHz OR
125MHz
1 × 33.33MHz
FORCE_LOW

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AD9571ACPZLVD Summary of contents

Page 1

FEATURES Fully integrated VCO/PLL core 0.17 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz 0.41 ps rms jitter from 12 kHz to 20 MHz at 125 MHz Input crystal or clock frequency of 25 MHz Preset ...

Page 2

AD9571 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 PLL Characteristics ...................................................................... 3 LVDS Clock Output Jitter ............................................................ 4 LVPECL Clock Output Jitter ...

Page 3

SPECIFICATIONS PLL CHARACTERISTICS Typical (typ) is given for Table 1. Parameter PHASE NOISE CHARACTERISTICS PLL Noise (156.25 MHz LVDS Output kHz @ 10 kHz @ 100 kHz @ 1 MHz @ ...

Page 4

AD9571 Parameter PLL Noise (125 MHz LVPECL Output kHz @ 10 kHz @ 100 kHz @ 1 MHz @ 10 MHz @ 30 MHz PLL Noise (100 MHz LVPECL Output kHz @ 10 kHz @ 100 ...

Page 5

LVPECL CLOCK OUTPUT JITTER Typical (typ) is given for Table 3. Jitter Integration 125 MHz Bandwidth (Typ) 100 MHz 33.33 MHz = Off/On 12 kHz to 20 MHz 0.54 0.42/2.0 1.875 MHz to ...

Page 6

AD9571 CLOCK OUTPUTS Typical (typ) is given for V = 3.3 V ± 10 over full V and T (−40°C to +85°C) variation Table 6. Parameter LVPECL CLOCK OUTPUTS Output Frequency Output High Voltage (V ) ...

Page 7

CONTROL PINS Typical (typ) is given for V = 3.3 V ± 10 over full V and T (−40°C to +85°C) variation Table 8. Parameter Min INPUT CHARACTERISTICS REFSEL Pin Logic 1 Voltage 2.0 Logic 0 ...

Page 8

AD9571 TIMING DIAGRAMS DIFFERENTIAL 80% LVPECL 20 Figure 3. LVPECL Timing, Differential DIFFERENTIAL 80% LVDS 20 Figure 4. LVDS Timing, Differential Rev Page SINGLE-ENDED 80% CMOS 5pF ...

Page 9

ABSOLUTE MAXIMUM RATINGS Table 11. Parameter Rating VS to GND −0 +3.6 V REFCLK to GND −0 0.3 V BYPASSx to GND −0 0 GND −0.3 V ...

Page 10

AD9571 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NOTES SHORT TO PIN 36 SHORT TO PIN 14. 3. NOTE THAT THE EXPOSED PADDLE ON THIS PACKAGE IS AN ELECTRICAL CONNECTION AS WELL AS A THERMAL ENHANCEMENT. ...

Page 11

Pin No. Mnemonic FORCE_LOW The exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to function properly, the paddle must be ...

Page 12

AD9571 TYPICAL PERFORMANCE CHARACTERISTICS Both 100 MHz and 125 MHz outputs enabled; 33.33 MHz output disabled. –100 –110 –120 –130 –140 –150 –160 1k 10k 100k 1M FREQUENCY (Hz) Figure 7. 125 MHz Phase Noise –100 –110 –120 –130 –140 ...

Page 13

TERMINOLOGY Phase Jitter An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 degrees to 360 degrees for each cycle. Actual signals, however, display a certain amount of variation ...

Page 14

AD9571 THEORY OF OPERATION REFSEL VS XTAL OSC 1 0 REFCLK FREQUENCY DETECTOR AD9571 Figure 11 shows a block diagram of the AD9571. The chip consists of a PLL core, which is configured to generate the specific clock frequencies required ...

Page 15

Table 15. FREQSEL Definition Frequency Available from Pin 19 and Pin 20 FREQSEL (MHZ) 0 125 1 100 NC 125 3.5mA OUT OUT 3.5mA Figure 12. LVDS Output Simplified Equivalent Circuit The simplified equivalent circuits of the LVDS and LVPECL ...

Page 16

AD9571 The value of the resistor is dependent on the board design and timing requirements (typically 10 Ω to 100 Ω is used). CMOS outputs are limited in terms of the capacitive load or trace length that they can drive. ...

Page 17

... SEATING PLANE ORDERING GUIDE Model Temperature Range 1, 2 AD9571ACPZLVD −40°C to +85° AD9571ACPZLVD-RL −40°C to +85°C AD9571ACPZLVD- −40°C to +85°C AD9571ACPZPEC 1, 3 −40°C to +85° AD9571ACPZPEC-R7 −40°C to +85° AD9571ACPZPEC-RL −40°C to +85° ...

Page 18

AD9571 NOTES Rev Page ...

Page 19

NOTES Rev Page AD9571 ...

Page 20

AD9571 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07499-0-8/09(0) Rev Page ...

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