ADF4360-0BCPZ Analog Devices Inc, ADF4360-0BCPZ Datasheet - Page 10

• Manufacturer Part Number: ADF4360-0BCPZ
• Description: IC INTEGRATED SYNTH/VCO 24-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Distribution, Integer N Synthesizer (RF)r

Specifications of ADF4360-0BCPZ

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 2.725GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-LFCSP
• Frequency-max: 2.725GHz
• Pll Type: Frequency Synthesis
• Frequency: 2.725GHz
• Supply Current: 10mA
• Supply Voltage Range: 3V To 3.6V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 24
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4360-0EBZ1 - BOARD EVALUATION FOR ADF4360-0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADF4360-0
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4360 family allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. The full truth table is shown in Table 7. Figure 13 shows
the MUXOUT section in block diagram form.
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital and analog. Digital lock detect is active high. When LDP
in the R counter latch is set to 0, digital lock detect is set high
when the phase error on three consecutive phase detector cycles
is less than 15 ns.
With LDP set to 1, five consecutive cycles of less than 15 ns
phase error are required to set the lock detect. It stays set high
until a phase error of greater than 25 ns is detected on any sub-
sequent PD cycle.
The N-channel open-drain analog lock detect should be oper-
ated with an external pull-up resistor of 10 kΩ nominal. When a
lock has been detected, this output is high with narrow low-
going pulses.
INPUT SHIFT REGISTER
The ADF4360 family’s digital section includes a 24-bit input
shift register, a 14-bit R counter, and an 18-bit N counter,
comprised of a 5-bit A counter and a 13-bit B counter. Data is
clocked into the 24-bit shift register on each rising edge of CLK.
The data is clocked in MSB first. Data is transferred from the
shift register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. These are the two LSBs, DB1
and DB0, as shown in Figure 2.
The truth table for these bits is shown in Table 5. Table 6 shows
a summary of how the latches are programmed. Note that the
test mode latch is used for factory testing and should not be
programmed by the user.
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
Figure 13. MUXOUT Circuit
MUX
CONTROL
DGND
DV
DD
MUXOUT
Rev. A | Page 10 of 24
Table 5. C2 and C1 Truth Table
C2
0
0
1
1
VCO
The VCO core in the ADF4360 family uses eight overlapping
bands, as shown in Figure 14, to allow a wide frequency range to
be covered without a large VCO sensitivity (K
poor phase noise and spurious performance.
The correct band is chosen automatically by the band select
logic at power-up or whenever the N counter latch is updated. It
is important that the correct write sequence be followed at
power-up. This sequence is
1.
2.
3.
During band select, which takes five PFD cycles, the VCO V
is disconnected from the output of the loop filter and connected
to an internal reference voltage.
The R counter output is used as the clock for the band select logic
and should not exceed 1 MHz. A programmable divider is provided
at the R counter input to allow division by 1, 2, 4, or 8 and is con-
trolled by Bits BSC1 and BSC2 in the R counter latch. Where the
required PFD frequency exceeds 1 MHz, the divide ratio should be
set to allow enough time for correct band selection.
After band select, normal PLL action resumes. The nominal
value of K
has been selected (by programming DIV2 [DB22] high in the N
counter latch). The ADF4360 family contains linearization cir-
cuitry to minimize any variation of the product of I
R counter latch
Control latch
N counter latch
Control Bits
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
2200
V
is 56 MHz/V or 28 MHz/V, if divide-by-2 operation
C1
0
1
0
1
Figure 14. Frequency vs. V
2400
FREQUENCY (MHz)
Data Latch
Control Latch
R Counter
N Counter (A and B)
Test Mode Latch
2600
TUNE
, ADF4360-0
2800
V
) and resultant
CP
and K
3000
TUNE
V
.