ADF4107BRUZ Analog Devices Inc, ADF4107BRUZ Datasheet - Page 4

• Manufacturer Part Number: ADF4107BRUZ
• Description: IC SYNTH FREQ PLL 7GHZ 16-TSSOP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of ADF4107BRUZ

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 7GHz
• Divider/multiplier: No/No
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 7GHz
• Pll Type: Frequency Synthesis
• Frequency: 7GHz
• Supply Current: 15mA
• Supply Voltage Range: 2.7V To 3.3V
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADF4107
Parameter
NOISE CHARACTERISTICS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TIMING CHARACTERISTICS
AV
unless otherwise noted.
Table 2.
Parameter
t
t
t
t
t
t
1
2
1
2
3
4
5
6
Operating temperature range (B version) is −40°C to +85°C.
The B chip specifications are given as typical values.
Use a square wave for lower frequencies, below the minimum stated.
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
AV
AC-coupling ensures AV
Guaranteed by design. Sample tested to ensure compliance.
T
T
Guaranteed by design but not production tested.
Operating temperature range (B Version) is −40°C to +85°C.
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value)
and 10log(F
The phase noise is measured with the EVAL-ADF4107EB1 evaluation board and the HP8562E spectrum analyzer. The spectrum analyzer provides the REF
synthesizer (f
f
f
f
A
A
REFIN
REFIN
REFIN
ADF4107 Normalized Phase
Noise Floor
Phase Noise Performance
Spurious Signals
= 25°C; AV
= 25°C; AV
DD
DD
900 MHz Output
6400 MHz Output
6400 MHz Output
900 MHz Output
6400 MHz Output
6400 MHz Output
= DV
= 10 MHz; f
= 10 MHz; f
= 10 MHz; f
= DV
DD
= 3 V.
PFD
DD
DD
DD
REFOUT
). PN
10
= DV
= DV
= 3 V ± 10%, AV
PFD
PFD
PFD
= 10 MHz @ 0 dBm).
= 200 kHz; offset frequency = 1 kHz; f
= 200 kHz; offset frequency = 1 kHz; f
= 1 MHz; offset frequency = 1 kHz; f
SYNTH
DD
DD
= 3 V; P = 32; RF
= 3.3 V; R = 16,383; A = 63; B = 891; P = 32; RF
DD
= PN
12
12
13
14
13
14
/2 bias.
1
TOT
CLOCK
− 20logN −10logF
11
DATA
LE
LE
DD
IN
≤ V
= 7.0 GHz.
Limit
10
10
25
25
10
20
DB23 (MSB)
P
B Version
−219
−93
−76
−83
−90/−92
−65/−70
−70/−75
≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
2
(B Version)
PFD
.
RF
1
RF
RF
= 6400 MHz; N = 6400; loop BW = 100 kHz.
t
1
= 900 MHz; N = 4500; loop BW = 20 kHz.
= 6400 MHz; N = 32,000; loop BW = 20 kHz.
DB22
B Chips
(Typ)
−219
−93
−76
−83
−90/−92
−65/−70
−70/−75
t
2
IN
= 7.0 GHz.
Figure 2. Timing Diagram
2
Rev. A | Page 4 of 20
Unit
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc typ
dBc typ
dBc typ
DB2
Unit
ns min
ns min
ns min
ns min
ns min
ns min
t
3
DB1 (CONTROL
t
4
BIT C2)
Test Conditions/Comments
@ VCO output
@ 1 kHz offset and 200 kHz PFD frequency
@ 1 kHz offset and 200 kHz PFD frequency
@ 1 kHz offset and 1 MHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 1 MHz/2 MHz and 1 MHz PFD frequency
Test Conditions/Comments
DATA to CLOCK setup time
DATA to CLOCK hold time
CLOCK high duration
CLOCK low duration
CLOCK to LE setup time
LE pulse width
SET
= 5.1 kΩ, dBm referred to 50 Ω, T
(CONTROL BIT C1)
t
5
DB0 (LSB)
t
6
A
= T
MAX
IN
for the
to T
MIN
,