ADF4107BRUZ Analog Devices Inc, ADF4107BRUZ Datasheet - Page 10

• Manufacturer Part Number: ADF4107BRUZ
• Description: IC SYNTH FREQ PLL 7GHZ 16-TSSOP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of ADF4107BRUZ

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 7GHz
• Divider/multiplier: No/No
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 7GHz
• Pll Type: Frequency Synthesis
• Frequency: 7GHz
• Supply Current: 15mA
• Supply Voltage Range: 2.7V To 3.3V
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADF4107
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4107 allows the user to
access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. Figure 25 shows the full truth table. Figure 21 shows the
MUXOUT section in block diagram form.
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.
Digital lock detect is active high. When the lock detect
precision (LDP) bit in the R counter latch is set to 0, digital lock
detect is set high when the phase error on three consecutive
phase detector (PD) cycles is less than 15 ns. With LDP set to 1,
five consecutive cycles of less than 15 ns are required to set the
lock detect. It stays set high until a phase error of greater than
25 ns is detected on any subsequent PD cycle.
The N-channel open-drain analog lock detect should be
operated with an external pull-up resistor of 10 kΩ nominal.
When lock has been detected, this output becomes high with
narrow, low going pulses.
R DIVIDER
N DIVIDER
Figure 20. PFD Simplified Schematic and Timing (in Lock)
HI
HI
D2
D1
CLR1
CLR2
U2
U1
Q1
Q2
PROGRAMMABLE
UP
DOWN
ABP2
DELAY
ABP1
U3
CPGND
V
P
CHARGE
PUMP
Rev. A | Page 10 of 20
CP
ANALOG LOCK DETECT
INPUT SHIFT REGISTER
The ADF4107 digital section includes a 24-bit input shift
register, a 14-bit R counter, and a 19-bit N counter, comprising a
6-bit A counter and a 13-bit B counter. Data is clocked into the
24-bit shift register on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the shift register
to one of four latches on the rising edge of LE. The destination
latch is determined by the state of the two control bits (C2, C1)
in the shift register. These are the two LSBs, DB1 and DB0, as
shown in the timing diagram of Figure 2. The truth table for
these bits is shown in Table 5. Figure 22 shows a summary of
how the latches are programmed.
Table 5. C2, C1 Truth Table
Control Bits
C2
0
0
1
1
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
C1
0
1
0
1
SDOUT
Data Latch
R Counter
N Counter (A and B)
Function Latch (Including Prescaler)
Initialization Latch
Figure 21. MUXOUT Circuit
MUX
CONTROL
DGND
DV
DD
MUXOUT