ADF4107BRUZ Analog Devices Inc, ADF4107BRUZ Datasheet - Page 18

• Manufacturer Part Number: ADF4107BRUZ
• Description: IC SYNTH FREQ PLL 7GHZ 16-TSSOP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of ADF4107BRUZ

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 7GHz
• Divider/multiplier: No/No
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 7GHz
• Pll Type: Frequency Synthesis
• Frequency: 7GHz
• Supply Current: 15mA
• Supply Voltage Range: 2.7V To 3.3V
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADF4107
APPLICATIONS
LOCAL OSCILLATOR FOR LMDS BASE STATION
TRANSMITTER
Figure 27 shows the ADF4107 being used with a VCO to
produce the LO for an LMDS base station.
The reference input signal is applied to the circuit at FREF
and, in this case, is terminated in 50 Ω. A typical base station
system has either a TCXO or an OCXO driving the reference
input without any 50 Ω termination.
To have a channel spacing of 1 MHz at the output, the 10 MHz
reference input must be divided by 10, using the on-chip
reference divider of the ADF4107.
The charge pump output of the ADF4107 (Pin 2) drives the
loop filter. In calculating the loop filter component values, a
number of items need to be considered. In this example, the
loop filter was designed so that the overall phase margin for the
system would be 45°.
FREF
IN
1000pF
51Ω
5.1kΩ
1000pF
1
8
CE
CLK
DATA
LE
AV
REF
3
R
V
Figure 27. 6.3 GHz Local Oscillator Using the ADF4107
7
DD
SET
DD
ADF4107
IN
4
DV
MUXOUT
15
DD
9
RF
RF
IN
IN
CP
V
V
16
A
B
P
P
IN
14
2
6
5
Rev. A | Page 18 of 20
100pF
100pF
100pF
LOCK
DETECT
NOTES:
1. DECOUPLING CAPACITORS (0.1µF/10pF) ON AV
V
BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
P
OF THE ADF4106 AND ON V
51Ω
Other PLL system specifications are:
K
K
Loop bandwidth = 70 kHz
F
N = 6300
Extra reference spur attenuation = 10 dB
All of these specifications are needed and used to derive the
loop filter component values shown in Figure 27.
Figure 27 gives a typical phase noise performance of −83 dBc/Hz
at 1 kHz offset from the carrier. Spurs are better than −70 dBc.
The loop filter output drives the VCO, which, in turn, is fed
back to the RF input of the PLL synthesizer and also drives the
RF output terminal. A T-circuit configuration provides 50 Ω
matching between the VCO output, the RF output, and the RF
terminal of the synthesizer.
In a PLL system, it is important to know when the system is in
lock. In Figure 27, this is accomplished by using the MUXOUT
signal from the synthesizer. The MUXOUT pin can be
programmed to monitor various internal signals in the
synthesizer. One of these is the LD or lock detect signal.
7.5kΩ
820pF
PFD
D
V
1.7kΩ
= 5.0 mA
= 80 MHz/V
= 1 MHz
47pF
2
V956ME01
V
14
CC
CC
1, 3, 4, 5, 7, 8,
9, 11, 12, 13
OF THE V956ME03 HAVE
10
100pF
DD
, DV
100pF
18Ω
DD
, AND
18Ω
18Ω
RF
OUT
IN