ICS854S204BGILF IDT, Integrated Device Technology Inc, ICS854S204BGILF Datasheet - Page 7

• Manufacturer Part Number: ICS854S204BGILF
• Description: IC CLK FANOUT BUFFER 1:2 16TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Buffer (Distribution)r

Specifications of ICS854S204BGILF

• Number Of Circuits: 2
• Ratio - Input:output: 1:2
• Differential - Input:output: Yes/Yes
• Input: CML, LVDS, LVPECL, SSTL
• Output: LVDS, LVPECL
• Frequency - Max: 3GHz
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 3GHz
• Number Of Outputs: 8
• Operating Supply Voltage (max): 3.465V
• Operating Temp Range: -40C to 85C
• Propagation Delay Time: 0.5ns
• Operating Supply Voltage (min): 2.375V
• Mounting: Surface Mount
• Pin Count: 16
• Operating Supply Voltage (typ): 2.5/3.3V
• Package Type: TSSOP
• Duty Cycle: 51%
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1964-5; 854S204BGILF; ICS854S204BGILF

IDT
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
ICS854S204I
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
™
/ ICS
™
LVDS, LVPECL FANOUT BUFFER
A
DDITIVE
O
FFSET
F
ROM
P
HASE
7
C
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
ARRIER
J
ITTER
F
REQUENCY
(H
Z
)
ICS854S204BGI REV. A JUNE 4, 2008
Input/Output Additive
Phase Jitter
= 0.12ps (typical)
at 100MHz