ICS854S204BGILF IDT, Integrated Device Technology Inc, ICS854S204BGILF Datasheet - Page 10

• Manufacturer Part Number: ICS854S204BGILF
• Description: IC CLK FANOUT BUFFER 1:2 16TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Buffer (Distribution)r

Specifications of ICS854S204BGILF

• Number Of Circuits: 2
• Ratio - Input:output: 1:2
• Differential - Input:output: Yes/Yes
• Input: CML, LVDS, LVPECL, SSTL
• Output: LVDS, LVPECL
• Frequency - Max: 3GHz
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 3GHz
• Number Of Outputs: 8
• Operating Supply Voltage (max): 3.465V
• Operating Temp Range: -40C to 85C
• Propagation Delay Time: 0.5ns
• Operating Supply Voltage (min): 2.375V
• Mounting: Surface Mount
• Pin Count: 16
• Operating Supply Voltage (typ): 2.5/3.3V
• Package Type: TSSOP
• Duty Cycle: 51%
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1964-5; 854S204BGILF; ICS854S204BGILF

W
IDT
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
R
I
PCLK/nPCLK I
For applications not requiring the use of the differential input,
both PCLK and nPCLK can be left floating. Though not required,
but for additional protection, a 1k resistor can be tied from PCLK
to ground.
NPUTS
ICS854S204I
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
ECOMMENDATIONS FOR
IRING THE
™
/ ICS
:
™
LVDS, LVPECL FANOUT BUFFER
D
NPUTS
IFFERENTIAL
U
I
NUSED
NPUT TO
F
IGURE
Single Ended Clock Input
I
NPUT AND
A
CCEPT
1. S
A
PPLICATION
INGLE
O
S
INGLE
UTPUT
C1
0.1u
E
NDED
V_REF
DD
E
/2 is
P
NDED
S
INS
IGNAL
10
I
L
NFORMATION
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
and R2/R1 = 0.609.
O
LVDS O
All unused LVDS output pairs can be either left floating or
terminated with 100
be no trace attached.
LVPECL O
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
R1
1K
R2
1K
D
EVELS
UTPUTS
V
RIVING
DD
PCLK
nPCLK
UTPUTS
D
:
UTPUTS
IFFERENTIAL
across. If they are left floating, there should
I
NPUT
ICS854S204BGI REV. A JUNE 4, 2008
DD
= 3.3V, V_REF should be 1.25V