ICS85211BMI-03LN IDT, Integrated Device Technology Inc, ICS85211BMI-03LN Datasheet - Page 7

• Manufacturer Part Number: ICS85211BMI-03LN
• Description: IC CLK FANOUT BUFFER 1:2 8SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Buffer (Distribution)r

Specifications of ICS85211BMI-03LN

• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: Yes/Yes
• Input: HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: LVHSTL
• Frequency - Max: 700MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC
• Frequency-max: 700MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1959-5; 85211BMI-03LN; ICS85211BMI-03LN

Application Information
Recommendations for Unused Output Pins
Outputs:
LVHSTL Outputs
All unused LVHSTL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage V
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as close
to the input pin as possible. The ratio of R1 and R2 might need to be
adjusted to position the V
For example, if the input clock swing is 2.5V and V
R2 value should be adjusted to set V
are for when both the single ended swing and V
voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
ICS85211BI-03 Data Sheet
ICS85211BMI-03 REVISION C MARCH 12, 2010
REF
in the center of the input voltage swing.
REF
REF
= V
at 1.25V. The values below
CC
/2 is generated by the
CC
CC
are at the same
= 3.3V, R1 and
7
line impedance. For most 50Ω applications, R3 and R4 can be 100Ω.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however V
than -0.3V and V
of the recommended components might not be used, the pads should
be placed in the layout. They can be utilized for debugging purposes.
The datasheet specifications are characterized and guaranteed by
using a differential signal.
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
IH
cannot be more than V
©2010 Integrated Device Technology, Inc.
CC
+ 0.3V. Though some
IL
cannot be less