ICS8305AGLF IDT, Integrated Device Technology Inc, ICS8305AGLF Datasheet - Page 12

• Manufacturer Part Number: ICS8305AGLF
• Description: IC CLK FAN BUFF MUX 2:4 16TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Fanout Buffer (Distribution), Multiplexerr
• Series: HiPerClockS™r

Specifications of ICS8305AGLF

• Number Of Circuits: 1
• Ratio - Input:output: 2:4
• Differential - Input:output: Yes/No
• Input: HCSL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL, SSTL
• Output: LVCMOS, LVTTL
• Frequency - Max: 350MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 350MHz
• Number Of Clock Inputs: 2
• Output Frequency: 350MHz
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1110; 800-1110-5; 800-1110; 8305AGLF

Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both signals must meet the V
V
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
Figure 3A. HiPerClockS CLK/nCLK Input
Figure 3C. HiPerClockS CLK/nCLK Input
Figure 3E. HiPerClockS CLK/nCLK Input
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
CMR
ICS8305
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
2.5V
input requirements. Figures 3A to 3F show interface
1.8V
3.3V
HCSL
LVPECL
*Optional – R3 and R4 can be 0
LVHSTL
IDT
HiPerClockS
LVHSTL Driver
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Driven by a 3.3V LVPECL Driver
Driven by a 3.3V HCSL Driver
*R3
*R4
Zo = 50
Zo = 50
Zo = 50
Zo = 50
33
33
Zo = 50
Zo = 50
R3
125
R1
50
3.3V
R1
84
R1
50
R4
125
R2
50
R2
84
R2
50
CLK
nCLK
CLK
nCLK
CLK
nCLK
3.3V
3.3V
3.3V
HiPerClockS
Input
HiPerClockS
Input
HiPerClockS
Input
PP
and
12
component to confirm the driver termination requirements. For
example, in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
Figure 3B. HiPerClockS CLK/nCLK Input
Figure 3D. HiPerClockS CLK/nCLK Input
Figure 3F. HiPerClockS CLK/nCLK Input
2.5V
3.3V
3.3V
SSTL
LVDS
LVPECL
Driven by a 3.3V LVPECL Driver
Driven by a 3.3V LVDS Driver
Driven by a 2.5V SSTL Driver
Zo = 60
Zo = 60
Zo = 50
Zo = 50
ICS8305AG REV. C OCTOBER 23, 2008
Zo = 50
Zo = 50
R3
120
2.5V
R1
120
R1
50
R2
50
R4
120
R2
120
R2
50
R1
100
CLK
nCLK
CLK
nCLK
CLK
nCLK
3.3V
3.3V
HiPerClockS
3.3V
HiPerClockS
Input
Receiver