ICS8305AGLF IDT, Integrated Device Technology Inc, ICS8305AGLF Datasheet - Page 11

• Manufacturer Part Number: ICS8305AGLF
• Description: IC CLK FAN BUFF MUX 2:4 16TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Fanout Buffer (Distribution), Multiplexerr
• Series: HiPerClockS™r

Specifications of ICS8305AGLF

• Number Of Circuits: 1
• Ratio - Input:output: 2:4
• Differential - Input:output: Yes/No
• Input: HCSL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL, SSTL
• Output: LVCMOS, LVTTL
• Frequency - Max: 350MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 350MHz
• Number Of Clock Inputs: 2
• Output Frequency: 350MHz
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1110; 800-1110-5; 800-1110; 8305AGLF

Application Information
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS_CLK Input
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the LVCMOS_CLK input to ground.
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to
ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
Figure 2. Single-Ended Signal Driving Differential Input
ICS8305
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Single Ended Clock Input
C1
0.1u
V_REF
R1
1K
R2
1K
V
DD
CLK
nCLK
DD
/2 is
11
Outputs:
LVCMOS Outputs
All unused LVCMOS output can be left floating. There should be no
trace attached.
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
R2/R1 = 0.609.
ICS8305AG REV. C OCTOBER 23, 2008
DD
= 3.3V, V_REF should be 1.25V and