IDT5T93GL02PGGI IDT, Integrated Device Technology Inc, IDT5T93GL02PGGI Datasheet - Page 8

• Manufacturer Part Number: IDT5T93GL02PGGI
• Description: IC CLK BUFF/DVR MUX 1:2 20TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: TERABUFFER™ IIr
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of IDT5T93GL02PGGI

• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: Yes/Yes
• Input: CML, eHSTL, HSTL, LVDS, LVEPECL, LVPECL, LVTTL
• Output: LVDS
• Frequency - Max: 450MHz
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 450MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 5T93GL02PGGI; 800-1986-5; IDT5T93GL02PGGI

IDT5T93GL02 Data Sheet
Table 5E. AC Differential Input Characteristics
NOTE 1.The output will not change state until the inputs have crossed and the minimum differential voltage range defined by V
met or exceeded.
NOTE 2.V
“complement” input level. The AC differential voltage must be achieved to guarantee switching to a new state.
NOTE 3.V
Table 5E. AC Characteristics
NOTE 1. AC propagation measurements should not be taken within the first 100 cycles of startup.
NOTE 2. Skew measured between crosspoints of all differential output pairs under identical input and output interfaces, transitions and load
conditions on any one device.
NOTE 3. Skew measured is the difference between propagation delay times tp
and output interfaces, transitions and load conditions on any one device.
NOTE 4. Skew measured is the magnitude of the difference in propagation times between any single differential output pair of two devices,
given identical transitions and load conditions at identical V
NOTE 5. All parameters are tested with a 50% input duty cycle.
NOTE 6. Guaranteed by design but not production tested.
IDT5T93GL02 REVISION B AUGUST 27, 2009
Symbol
V
V
V
V
Symbol
tsk(o)
tsk(p)
tsk(pp)
tp
tp
fo
t
t
t
t
t
PGE
PGD
PWRDN
PWRUP
R
DIF
X
CM
IN
LH
HL
/ t
F
DIF
CM
Parameter
AC Differential Voltage
Differential Input Cross Point Voltage
Common Mode Input Voltage Range
Input Voltage
Parameter
Same Device Output Pin-to-Pin Skew
Pulse Skew
Part-to-Part Skew
Propagation Delay, Low-to-High
Propagation Delay, High-to-Low
Frequency Range
Output Gate Enable Crossing
VTHI-to-Qn/Qn Crosspoint
Output Gate Enable Crossing
VTHI-to-Qn/Qn Crosspoint Driven to
GL Designated Level
PD Crossing V
Output Gate Disable Crossing V
Qn/Qn Driven to Designated Level
Output Rise/Fall Time
specifies the minimum input voltage (V
specifies the maximum allowable range of (V
(3)
THI
-to-Qn = V
(4)
(6)
(1,5)
(6)
(2)
, T
A
DD
= -40°C to 85°C
, Qn = V
THI
to
(3)
(2)
DD
TR
(1)
– V
, T
TR
CP
DD
A
A Crosspoint to Qn/Qn
) required for switching where V
+ V
= -40°C to 85°C
levels and temperature.
Test Conditions
CP
20% to 80%
Crosspoint
) /2.
8
HL
and tp
Minimum
2.5V LVDS 1:2 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
0.05
0.05
-0.3
0.1
LH
Minimum
of any differential output pair under identical input
100
TR
is the “true” input level and V
Typical
Typical
©2009 Integrated Device Technology, Inc.
1.5
1.5
Maximum
Maximum
V
V
3.6
3.6
DD
DD
100
300
450
100
100
500
2.2
2.2
3.5
3.5
50
CP
DIF
is the
has been
Units
Units
MHz
V
V
V
V
µS
µS
ps
ps
ps
ns
ns
ns
ns
ps