IDT5T93GL02PGGI IDT, Integrated Device Technology Inc, IDT5T93GL02PGGI Datasheet - Page 3

• Manufacturer Part Number: IDT5T93GL02PGGI
• Description: IC CLK BUFF/DVR MUX 1:2 20TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: TERABUFFER™ IIr
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of IDT5T93GL02PGGI

• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: Yes/Yes
• Input: CML, eHSTL, HSTL, LVDS, LVEPECL, LVPECL, LVTTL
• Output: LVDS
• Frequency - Max: 450MHz
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 450MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 5T93GL02PGGI; 800-1986-5; IDT5T93GL02PGGI

IDT5T93GL02 Data Sheet
Table 1. Pin Descriptions
NOTES:
1.
2.
3.
4.
Table 2. Pin Characteristics
NOTE: This parameter is measured at characterization but not tested.
IDT5T93GL02 REVISION B AUGUST 27, 2009
Symbol
C
IN
Name
Q[1:2]
Q[1:2]
A[1:2]
A[1:2]
FSEL
GND
SEL
V
PD
GL
no input signal.
Inputs are capable of translating the following interface standards:
Single-ended 3.3V and 2.5V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL (2.5V) and LVPECL (3.3V) levels
Differential LVDS levels
Differential CML levels
Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control
signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry.
It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain
disabled until the device completes power-up after asserting PD.
The user must take precautions with any differential input interface standard being used in order to prevent instability when there is
G
DD
Parameter
Input Capacitance
Output
Output
Input
Input
Input
Input
Input
Input
Input
Type
Adjustable
Adjustable
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Power
Power
LVDS
LVDS
(1, 4)
(1, 4)
(T
Description
Clock input. A
Complementary clock inputs. A[1:2] is the complementary side of A[1:2]
For LVTTL single-ended operation, A[1:2] should be set to the desired toggle voltage for
A[1:2]:
3.3V LVTTL V
2.5V LVTTL V
Gate control for differential outputs Q1 and Q1 through Q2 and Q2. When G is LOW, the
differential outputs are active. When G is HIGH, the differential outputs are asynchronously
driven to the level designated by GL
Specifies output disable level. If HIGH, "true" outputs disable HIGH and "complementary"
outputs disable LOW. If LOW, "true" outputs disable LOW
and "complementary" outputs disable HIGH.
Clock outputs.
Complementary clock outputs.
Reference clock select. When LOW, selects A2 and A2.
When HIGH, selects A1 and A1.
Power-down control. Shuts off entire chip. If LOW, the device goes into low power mode.
Inputs and outputs are disabled. Both "true" and "complementary" outputs will pull to V
Set HIGH for normal operation.
At a rising edge, FSEL forces select to the input designated by SEL.
Set LOW for normal operation. At power-up, FSEL should be LOW.
Power supply for the device core and inputs.
Ground.
A
= +25°C, F = 1.0MHz)
Test Conditions
[1:2]
REF
REF
is the "true" side of the differential clock input.
= 1650mV
= 1250mV
3
(3)
(2)
2.5V LVDS 1:2 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
.
Minimum
Typical
©2009 Integrated Device Technology, Inc.
Maximum
3
.
Units
pF
DD
.