IDT5T93GL02PGGI IDT, Integrated Device Technology Inc, IDT5T93GL02PGGI Datasheet - Page 11

• Manufacturer Part Number: IDT5T93GL02PGGI
• Description: IC CLK BUFF/DVR MUX 1:2 20TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: TERABUFFER™ IIr
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of IDT5T93GL02PGGI

• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: Yes/Yes
• Input: CML, eHSTL, HSTL, LVDS, LVEPECL, LVPECL, LVTTL
• Output: LVDS
• Frequency - Max: 450MHz
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 450MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 5T93GL02PGGI; 800-1986-5; IDT5T93GL02PGGI

IDT5T93GL02 Data Sheet
FSEL Operation for When Opposite Clock Dies
1. When the differential on the non-selected clock goes below the minimum DC differential, the outputs clock goes to an unknown state. When
this happens, the FSEL pin should be asserted in order to force selection of the new input clock. The output clock will start up after a number
of cycles of the newly-selected input clock.
2. The FSEL pin should stay asserted until the problem with the dead clock can be fixed in the system.
3. It is recommended that the FSEL be tied HIGH for systems that use only one input. If this is not possible, the user must guarantee that the
unused input have a differential greater than or equal to the minimum DC differential specified in the datasheet.
Selection of Input While Protecting Against When Opposite Clock Dies
1. If the user holds FSEL HIGH, the output will not be affected by the deselected input clock.
2. The output will immediately be driven to LOW once FSEL is asserted. This may cause glitching on the output. The output will restart with
the input clock selected by the SEL pin.
3. If the user decides to switch input clocks, the user must de-assert FSEL, then assert FSEL after toggling the SEL input pin. The output will
be driven LOW and will restart with the input clock selected by the SEL pin.
IDT5T93GL02 REVISION B AUGUST 27, 2009
Qn - Qn
A
A
FSEL
1
2
SEL
- A
- A
1
2
11
2.5V LVDS 1:2 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
©2009 Integrated Device Technology, Inc.
+V
V
-V
+V
V
-V
+V
V
-V
V
V
V
V
V
V
DIF
DIF
DIF
DIF
DIF
DIF
THI
THI
IH
IL
IH
IL
DIF
DIF
DIF
=0
=0
=0