ICS952906AFLF IDT, Integrated Device Technology Inc, ICS952906AFLF Datasheet - Page 10

• Manufacturer Part Number: ICS952906AFLF
• Description: IC TIMING CTRL HUB P4 48-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Timing Control Hubr

Specifications of ICS952906AFLF

• Input: Crystal
• Output: Clock
• Frequency - Max: 460MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Frequency-max: 460MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 952906AFLF

1236A—08/06/07
Table 5: Asynchronous 3V66/PCI Frequency Table
I
I
Table 4: Mode Selection Table
Mode
IIC Control
25MHz From?
3V66/PCI From?
Spreading
I
2
2
2
C Table: Output Control Register
C Table: Reserved Register
C Table: Vendor & Revision ID Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte 4
Byte 5
Byte 6
Integrated
Circuit
Systems, Inc.
Byte6 Bit7
0
0
1
29
25
9
8
7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Pin #
Pin #
Pin #
2x output drive
Standard Overclock Mode(I)
Byte 5 bit(6:5) = 00
PLL3
PLL1 (Needed to be align w/ CPU)
CPU/3V66/PCI have spread
M PLL2 Div3
M PLL2 Div2
M PLL2 Div1
M PLL2 Div0
N PLL2 Div6
N PLL2 Div5
N PLL2 Div4
N PLL2 Div3
N PLL2 Div2
N PLL2 Div1
N PLL2 Div0
PCICLK_F2
PCICLK_F1
PCICLK_F0
Mode Sel1
Mode Sel0
Reserved
Reserved
Reserved
48MHz_0
PCI ADIV
3V66_0
3V66_2
ASEL0
Name
Name
Name
Byte3 Bit7
3V66/PCI Freq Select
Programming bits for
Programming bits for
PLL Mode Selection
PCI Async Divider
0
1
0
Async mode 2&3
Async mode 2&3
Output Control
Output Control
Output Control
Output Control
Output Control
0=2x drive
Function
Reserved
Reserved
Function
Reserved
Function
M Divider
N Divider
Control
Control
Control
Cntr
Bits
10
CPU Overclock Mode(II)
Byte 5 bit(6:5) = 01
PLL3
PLL3
Only CPU clocks have spread.
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
3V66/PCI Frequency
The decimal representation of M PLL2 Div
The decimal representation of N PLL2 Div
See Table 5: Async AGP/PCI Freq Table
(6:0) + 8 is equal to VCO divider value for
(3:0) + 2 is equal to REF divider value for
66.66/33.33
80.00/40.00
72.73/36.36
See Table 4: Mode Selection Table
2x drive
Disable
Disable
Disable
Disable
Disable
AGP/2
0
0
0
-
-
-
PLL2.
PLL2
Graphic Overclock Mode(III)
Byte 5 bit(6:5) = 10
PLL1
PLL3
Only CPU clocks have spread.
PLL3 Freq/24
normal
Enable
Enable
Enable
Enable
Enable
1
1
1
-
-
-
ICS952906A
PWD
PWD
PWD
1
0
1
1
1
1
1
1
0
0
0
1
X
X
X
X
0
X
X
X
X
X
X
X