ICS9LPRS365BKLF IDT, Integrated Device Technology Inc, ICS9LPRS365BKLF Datasheet
ICS9LPRS365BKLF
Specifications of ICS9LPRS365BKLF
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ICS9LPRS365BKLF Summary of contents
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CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor Recommended Application: CK505 compliant clock with fully integrated voltage regulator and Internal series resistor on differential outputs Output Features: • CPU differential low power push-pull pairs • 9 ...
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TSSOP Pin Description PIN # PIN NAME 1 PCI0/CR#_A 2 VDDPCI 3 PCI1/CR#_B 4 PCI2/TME 5 PCI3 6 PCI4/27_Select 7 PCI_F5/ITP_EN 8 GNDPCI 9 VDD48 10 USB_48MHz/FSLA 11 GND48 12 VDD96_IO 13 DOTT_96/SRCT0 14 DOTC_96/SRCC0 15 GND 16 VDD 1218—09/01/10 ...
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TSSOP Pin Description (Continued) PIN # PIN NAME 27MHz_NonSS/SRCT1/SE1 17 27MHz_SS/SRCC1/SE2 18 19 GND 20 VDDPLL3_IO 21 SRCT2/SATAT 22 SRCC2/SATAC 23 GNDSRC 24 SRCT3/CR#_C 25 SRCC3/CR#_D 26 VDDSRC_IO 27 SRCT4 28 SRCC4 29 GNDSRC 30 SRCT9 31 SRCC9 32 SRCC11/CR#_G ...
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TSSOP Pin Description (Continued) PIN # PIN NAME 33 SRCT11/CR#_H 34 SRCT10 35 SRCC10 36 VDDSRC_IO 37 CPU_STOP# 38 PCI_STOP# 39 VDDSRC 40 SRCC6 41 SRCT6 42 GNDSRC 43 SRCC7/CR#_E 44 SRCT7/CR#_F 45 VDDSRC_IO 46 CPUC2_ITP/SRCC8 47 CPUT2_ITP/SRCT8 48 NC ...
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TSSOP Pin Description (Continued) PIN # PIN NAME 49 VDDCPU_IO 50 CPUC1_F 51 CPUT1_F 52 GNDCPU 53 CPUC0 54 CPUT0 55 VDDCPU 56 CK_PWRGD/PD# 57 FSLB/TEST_MODE 58 GNDREF VDDREF 62 REF0/FSLC/TEST_SEL 63 SDATA 64 SCLK ...
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Pin Configuration GNDREF VDDREF 4 REF0/FSLC/TEST_SEL 5 SDATA 6 SCLK 7 PCI0/CR#_A 8 VDDPCI 9 PCI1/CR#_B 10 PCI2/TME 11 PCI3 12 PCI4/27_Select 13 PCI_F5/ITP_EN 14 GNDPCI 15 VDD48 ...
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MLF Pin Description PIN # PIN NAME 1 GNDREF VDDREF 5 REF0/FSLC/TEST_SEL 6 SDATA 7 SCLK 8 PCI0/CR#_A 9 VDDPCI 10 PCI1/CR#_B 11 PCI2/TME 12 PCI3 13 PCI4/27_Select 14 PCI_F5/ITP_EN 15 GNDPCI 16 VDD48 1218—09/01/10 ...
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MLF Pin Description (Continued) PIN # PIN NAME 17 USB_48MHz/FSLA 18 GND48 19 VDD96_IO 20 DOTT_96/SRCT0 21 DOTC_96/SRCC0 22 GND 23 VDD 27MHz_NonSS/SRCT1/SE1 24 27MHz_SS/SRCC1/SE2 25 26 GND 27 VDDPLL3_IO 28 SRCT2/SATAT 29 SRCC2/SATAC 30 GNDSRC 31 SRCT3/CR#_C 32 SRCC3/CR#_D ...
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MLF Pin Description (Continued) PIN # PIN NAME 33 VDDSRC_IO 34 SRCT4 35 SRCC4 36 GNDSRC 37 SRCT9 38 SRCC9 39 SRCC11/CR#_G 40 SRCT11/CR#_H 41 SRCT10 42 SRCC10 43 VDDSRC_IO 44 CPU_STOP# 45 PCI_STOP# 46 VDDSRC 47 SRCC6 48 SRCT6 ...
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MLF Pin Description (Continued) PIN # PIN NAME 49 GNDSRC 50 SRCC7/CR#_E 51 SRCT7/CR#_F 52 VDDSRC_IO 53 CPUC2_ITP/SRCC8 54 CPUT2_ITP/SRCT8 VDDCPU_IO 57 CPUC1_F 58 CPUT1_F 59 GNDCPU 60 CPUC0 61 CPUT0 62 VDDCPU 63 CK_PWRGD/PD# 64 FSLB/TEST_MODE ...
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General Description ICS9LPRS365 follows Intel CK505 Yellow Cover specification. This clock synthesizer provides a single chip solution for next generation P4 Intel processors and Intel chipsets. ICS9LPRS365 is driven with a 14.318MHz crystal. It also provides a tight ppm accuracy ...
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Absolute Maximum Ratings PARAMETER SYMBOL Maximum Supply Voltage VDDxxx Maximum Supply Voltage VDDxxx_IO Maximum Input Voltage Minimum Input Voltage Storage Temperature Case Temperature Input ESD protection ESD prot 1 Guaranteed by design and characterization, not 100% tested in production. 2 ...
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Electrical Characteristics - SMBus Interface PARAMETER SYMBOL SMBus Voltage Low-level Output Voltage V Current sinking 0.4 V OLSMB SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time Maximum SMBus Operating F Frequency 1 Guaranteed by design and ...
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Electrical Characteristics - PCICLK/PCICLK_F PARAMETER SYMBOL Long Accuracy Clock period Absolute min/max period Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Duty Cycle Skew Intentional PCI-PCI delay Jitter, ...
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Electrical Characteristics - USB48MHz PARAMETER SYMBOL Long Accuracy Clock period Absolute min/max period Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Duty Cycle Jitter, Cycle to cycle t ...
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Electrical Characteristics - REF-14.318MHz PARAMETER SYMBOL Long Accuracy Clock period Absolute min/max period Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Duty Cycle Jitter t 1 Guaranteed by ...
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Table 1: CPU Frequency Select Table CPU MHz B0b7 B0b6 B0b5 266. 133. 200. 166.66 1 ...
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Table 3: IO_Vout select table B9b2 B9b1 B9b0 IO_Vout ...
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General SMBus serial interface information for the ICS9LPRS365 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends the beginning byte location = ...
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Byte 0 FS Readback and PLL Selection Register Bit Pin Name 7 FSLC CPU Freq. Sel. Bit (Most Significant FSLB 5 FSLA CPU Freq. Sel. Bit (Least Significant) - Set via SMBus or dynamically by CK505 if ...
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Byte 4 Output Enable and Spread Spectrum Disable Register Bit Pin Name 7 SRC3_OE 6 SATA/SRC2_OE 5 SRC1_OE 4 SRC0/DOT96_OE 3 CPU1_OE 2 CPU0_OE 1 PLL1_SSC_ON 0 PLL3_SSC_ON Byte 5 Clock Request Enable/Configuration Register Bit Pin Name 7 CR#_A_EN PCI0_OE ...
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Byte 8 Device ID and Output Enable Register Bit Pin Name 7 Device_ID3 Table of Device identifier codes, used for 6 Device_ID2 differentiating between CK505 package options, 5 Device_ID1 4 Device_ID0 3 Reserved 2 Reserved 1 SE1_OE 0 SE2_OE Byte ...
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Byte 12 Byte Count Register Bit Pin Name 7 Reserved 6 Reserved 5 BC5 4 BC4 3 BC3 2 BC2 1 BC1 0 BC0 Byte 13 VCO Frequency Control Register PLL1 Bit Pin Name 7 N Div8 6 N Div9 ...
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Byte 17 VCO Frequency Control Register PLL3 Bit Pin Name 7 N Div8 6 N Div9 5 M Div5 4 M Div4 The decimal representation of M Div (5:0) is equal 3 M Div3 to reference divider value. Default at ...
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Test Clarification Table Comments Power-up w/ TEST_SEL = 1 to enter test mode Cycle power to disable test mode FSLC./TEST_SEL -->3-level latched input If power-up w/ V>2.0V then use TEST_SEL If power-up w/ V<2.0V then use FSLC FSLB/TEST_MODE -->low Vth ...
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INDEX INDEX AREA AREA Marking Diagram 1218—09/01/10 c SYMBOL α aaa VARIATIONS ...
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THERMALLY ENHANCED THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE DIMENSIONS OPTION 1 DIMENSIONS (mm BASIC D2 MIN. / MAX. E2 MIN. / MAX. L ...
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Revision History Rev. Issue Date Description 0.1 4/5/2006 Initial Release 0.2 7/11/2006 Updated Electrical Characteristics. 0.3 8/25/2006 1. Updated pin description and I2C. 0.4 10/25/2006 Added Byte 21. 1. Updated pin description of pin #33 (TSSOP) and pin #40 (QFN) ...