ICS9LPRS365BKLF IDT, Integrated Device Technology Inc, ICS9LPRS365BKLF Datasheet - Page 5

• Manufacturer Part Number: ICS9LPRS365BKLF
• Description: IC CLK SYNTHESIZR CK505 64VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS9LPRS365BKLF

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: *
• Frequency-max: *
• Number Of Elements: 3
• Supply Current: 250mA
• Pll Input Freq (max): 14.318MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: VFQFPN EP
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 9LPRS365BKLF

TSSOP Pin Description (Continued)
1218—09/01/10
PIN #
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
VDDCPU_IO
CPUC1_F
CPUT1_F
GNDCPU
CPUC0
CPUT0
VDDCPU
CK_PWRGD/PD#
FSLB/TEST_MODE
GNDREF
X2
X1
VDDREF
REF0/FSLC/TEST_SEL
SDATA
SCLK
PIN NAME
TYPE
PWR
OUT
OUT
PWR
OUT
OUT
PWR
PWR
OUT
PWR
I/O
I/O
IN
IN
IN
IN
Complement clock of low power differenatial CPU clock pair. This clock will be free-running during iAMT.
True clock of low power differential CPU clock pair. This clock will be free-running during iAMT.
Ground Pin for CPU Outputs
Complement clock of low power differential CPU clock pair.
True clock of low power differential CPU clock pair.
Power Supply 3.3V nominal.
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in
test mode. Refer to Test Clarification Table.
Ground pin for crystal oscillator circuit
Crystal output, nominally 14.318MHz.
Crystal input, Nominally 14.318MHz.
Power pin for the REF outputs, 3.3V nominal.
3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency selection. Refer to
input electrical characteristics for Vil_FS and Vih_FS values/ TEST_SEL: 3-level latched input to enable
test mode. Refer to Test Clarification Table.
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
1.05V to 3.3V from external power supply
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and
5
DESCRIPTION
ICS9LPRS365
Datasheet