ics9lprs525 Integrated Device Technology, ics9lprs525 Datasheet
ics9lprs525
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ics9lprs525 Summary of contents
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... VDDPLL3IO 20 SRCT2_LRS/SATAT_LRS 21 SRCC2_LRS/SATAC_LRS 22 GNDSRC 23 SRCT3_LRS/CR#_C 24 SRCC3_LRS/CR#_D 25 VDDSRCIO 26 SRCT4_LRS 27 SRCC4_LRS 28 56-SSOP & TSSOP 1 ICS9LPRS525 Supports spread spectrum modulation -0.5% down spread Supports CPU clks up to 400MHz Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning CPU SRC ...
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... ICS9LPRS525 PC MAIN CLOCK Pin Description PIN # PIN NAME TYPE 1 PCI0/CR#_A I/O 2 VDDPCI PWR 3 PCI1/CR#_B I/O 4 PCI2/TME I/O 5 PCI3/CFG0 I/O 6 PCI4/SRC5_EN I/O 7 PCI_F5/ITP_EN I/O 8 GNDPCI PWR 9 VDD48 PWR 10 USB_48MHz/FSLA I/O 11 GND48 PWR 12 VDD96IO PWR 13 DOTT_96_LRS/SRCT0_LRS OUT 14 DOTC_96_LRS/SRCC0_LRS OUT 15 GND PWR 16 VDD PWR 17 SRCT1_LRS/SE1 OUT 18 SRCC1_LRS/SE2 OUT 19 GND PWR 20 VDDPLL3IO ...
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... ICS9LPRS525 PC MAIN CLOCK Pin Description (continued) PIN # PIN NAME TYPE 25 SRCC3_LRS/CR#_D I/O 26 VDDSRCIO PWR 27 SRCT4_LRS OUT 28 SRCC4_LRS OUT 29 CPU_STOP#/SRCC5_LRS I/O 30 PCI_STOP#/SRCT5_LRS I/O 31 VDDSRC PWR 32 SRCC6_LRS OUT 33 SRCT6_LRS OUT 34 GNDSRC PWR 35 SRCC7_LRS/CR#_E I/O 36 SRCT7_LRS/CR#_F I/O 37 VDDSRCIO PWR 38 CPUC2_ITP_LRS/SRCC8_LRS OUT 39 CPUT2_ITP_LRS/SRCT8_LRS OUT N VDDCPUIO PWR 42 CPUC1_F_LRS ...
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... PC MAIN CLOCK General Description ICS9LPRS525 is compliant Intel CK505 Yellow Cover specification. This clock synthesizer provides a single chip solution for Intel desktop chipsets. ICS9LPRS525 is driven with a 14.318MHz crystal. It also provides a tight ppm accuracy output for Serial ATA and PCI-Express support. Block Diagram ...
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... ICS9LPRS525 PC MAIN CLOCK Absolute Maximum Ratings - DC Parameters PARAMETER SYMBOL Maximum Supply Voltage VDDxxx Maximum Supply Voltage VDDxxx_IO Maximum Input Voltage Minimum Input Voltage Storage Temperature Case Temperature Input ESD protection ESD prot 1 Guaranteed by design and characterization, not 100% tested in production. 2 Operation under these conditions is neither implied, nor guaranteed. ...
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... ICS9LPRS525 PC MAIN CLOCK NOTES on Input/Supply/Common Output DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). 1 Signal is required to be monotonic in this region. 2 input leakage current does not include inputs with pull-up or pull-down resistors 3 3.3V referenced inputs are: PCI_STOP#, CPU_STOP#, TME, SRC5_EN, ITP_EN, SCLKL, SDATA, TESTMODE, TESTSEL, CKPWRGD and CR# inputs if selected. ...
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... ICS9LPRS525 PC MAIN CLOCK Differential Clock Tolerances CPU PPM tolerance 100 Cycle to Cycle Jitter 85 Spread -0.50% Clock Periods - Differential Outputs with Spread Spectrum Disabled 1 Clock Center SSC OFF Freq. -c2c jitter MHz AbsPer Min 100.00 9.91400 133.33 7.41425 166.67 5.91440 CPU 200.00 4.91450 266 ...
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... ICS9LPRS525 PC MAIN CLOCK Electrical Characteristics - PCICLK/PCICLK_F PARAMETER Long Accuracy Clock period Absolute min/max period Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Pin to Pin Skew Intential PCI to PCI delay ...
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... ICS9LPRS525 PC MAIN CLOCK Electrical Characteristics - REF-14.318MHz PARAMETER Long Accuracy Clock period Absolute min/max period CLK High Time CLK Low time Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate ...
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... ICS9LPRS525 PC MAIN CLOCK Table 1: CPU Frequency Select Table CPU MHz B0b7 B0b6 B0b5 266. 133. 200. 166. 333. 100. 400. and FS B are low-threshold inputs.Please see V ...
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... ICS9LPRS525 PC MAIN CLOCK Table 3: IO_Vout select table B9b2 B9b1 B9b0 IO_Vout 1.0V Table 4: Device ID table B8b7 B8b6 B8b5 B8b4 Table 5: Slew Rate Selection Table Bit 1 Bit 0 Slew Rate ...
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... ICS9LPRS525 PC MAIN CLOCK PCI_STOP# Power Management SMBus OE Bit PCI_STOP# 1 Enable 0 Disable X CPU_STOP# Power Management SMBus OE Bit PCI_STOP# 1 Enable 0 Disable X CR# Power Management SMBus OE Bit CR# 1 Enable 0 Disable X PD# Power Management Single-ended Clocks Device State w/o Latched input w/Latched input Latches Open Power Down ...
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... ICS9LPRS525 PC MAIN CLOCK General SMBus serial interface information for the ICS9LPRS525 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends the beginning byte location = N • ICS clock will acknowledge • ...
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... ICS9LPRS525 PC MAIN CLOCK Byte 0 FS Readback and PLL Selection Register Bit Pin Name 7 FSLC - 6 FSLB - 5 FSLA - 4 - iAMT_EN 3 Reserved 2 - SRC_Main_SEL 1 - SATA_SEL 0 - PD_Restore Byte 1 DOT96 Select and PLL3 Quick Config Register Bit Pin Name 7 13/14 SRC0_SEL 6 - PLL1_SSC_SEL 5 PLL3_SSC_SEL 4 PLL3_CF3 3 PLL3_CF2 2 PLL3_CF1 1 PLL3_CF0 0 PCI_SEL Byte 2 Output Enable Register ...
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... ICS9LPRS525 PC MAIN CLOCK Byte 4 Output Enable and Spread Spectrum Disable Register Bit Pin Name 7 SRC3_OE 6 SATA/SRC2_OE 5 SRC1_OE 4 SRC0/DOT96_OE 3 CPU1_OE 2 CPU0_OE 1 PLL1_SSC_ON 0 PLL3_SSC_ON Byte 5 Clock Request Enable/Configuration Register Bit Pin Name 7 CR#_A_EN 6 CR#_A_SEL 5 CR#_B_EN 4 CR#_B_SEL 3 CR#_C_EN 2 CR#_C_SEL 1 CR#_D_EN 0 CR#_D_SEL Byte 6 Clock Request Enable/Configuration and Stop Control Register ...
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... ICS9LPRS525 PC MAIN CLOCK Byte 8 Device ID and Output Enable Register Bit Pin Name 7 Device_ID3 6 Device_ID2 5 Device_ID1 4 Device_ID0 3 Reserved 2 Reserved 1 SE1_OE 0 SE2_OE Byte 9 Output Control Register Bit Pin Name 7 PCIF5 STOP EN 6 TME_Readback 5 REF Strength 4 Test Mode Select 3 Test Mode Entry 2 IO_VOUT2 1 IO_VOUT1 ...
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... ICS9LPRS525 PC MAIN CLOCK Byte 12 Byte Count Register Bit Pin Name 7 Reserved 6 Reserved 5 BC5 4 BC4 3 BC3 2 BC2 1 BC1 0 BC0 Byte Reserved Byte 29 Slew Rate Control Bit Pin Name 7 USB_Slew1 6 USB_Slew0 5 PCI_Slew1 4 PCI_Slew0 3 Reserved 2 REF Slew Rate 1 Reserved 0 Reserved PC MAIN CLOCK TM IDT ...
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... ICS9LPRS525 PC MAIN CLOCK Test Clarification Table Comments Power-up w/ TEST_SEL = 1 to enter test mode Cycle power to disable test mode FSLC./TEST_SEL -->3-level latched input If power-up w/ V>2.0V then use TEST_SEL If power-up w/ V<2.0V then use FSLC FSLB/TEST_MODE -->low Vth input TEST_MODE is a real time input If TEST_SEL HW pin is 0 during power-up, test mode can be invoked through B9b3 ...
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... ICS9LPRS525 PC MAIN CLOCK Ordering Information 9LPRS525AFLFT Example: XXXX MAIN CLOCK TM IDT SYMBOL VARIATIONS Reference Doc.: JEDEC Publication 95, MO-118 10-0034 Designation for tape and reel packaging Lead Free, RoHS Compliant Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) ...
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... ICS9LPRS525 PC MAIN CLOCK N E1 INDEX INDEX AREA AREA Ordering Information 9LPRS525AGLFT Example: XXXX MAIN CLOCK TM IDT c SYMBOL L E VARIATIONS - SEATING SEATING PLANE PLANE Reference Doc.: JEDEC Publicat ion 95, M O-153 aaa C 10-0039 Designation for tape and reel packaging ...
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... ICS9LPRS525 PC MAIN CLOCK Revision History Rev. Issue Date Description 0.1 7/21/2008 Initial Release 1. Updated pinout to remove Vout reference on pin 40 0.2 08/060/08 2. Updated VDD_IO pin descriptions to show 1.05V to 3.3V operation 1. Fixed Pagination of Pin Descriptions 2. Changed reference to PCI3 Config Table in Pindes to match table name 0.3 8/8/2008 3. Added Byte 29 for Slew Rate control 1) Byte 11, bit 5 is now reserved. 2) Byte 29, bits 7:6 default to 0.8X slew rate (‘ ...