ICS9DB803DGLF IDT, Integrated Device Technology Inc, ICS9DB803DGLF Datasheet
ICS9DB803DGLF
Specifications of ICS9DB803DGLF
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ICS9DB803DGLF Summary of contents
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Eight Output Differential Buffer for PCIe Gen 2 Description The ICS9DB803 is compatible with the Intel DB800v2 Differential Buffer Specification. This buffer provides 8 PCI- Express Gen2 clocks. The ICS9DB803 is driven by a differential output pair from a CK410B+, ...
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ICS9DB803D Eight Output Differential Buffer for PCIe for Gen 2 Pin Configuration SRC_DIV# 1 VDD 2 GND 3 SRC_IN 4 SRC_IN# 5 OE_0 6 OE_3 7 DIF_0 8 DIF_0# 9 GND 10 VDD 11 DIF_1 12 DIF_1# 13 OE_1 14 ...
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ICS9DB803D Eight Output Differential Buffer for PCIe for Gen 2 Pin Description for OE_INV = 0 PIN # PIN NAME PIN TYPE 1 SRC_DIV VDD PWR 3 GND PWR 4 SRC_IN IN 5 SRC_IN OE_0 IN ...
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ICS9DB803D Eight Output Differential Buffer for PCIe for Gen 2 Pin Description for OE_INV = 0 PIN # PIN NAME PIN TYPE 25 GND PWR 26 PD DIF_STOP HIGH_BW# PWR 29 DIF_4# OUT 30 DIF_4 OUT ...
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ICS9DB803D Eight Output Differential Buffer for PCIe for Gen 2 Pin Description for OE_INV = 1 PIN # PIN NAME PIN TYPE 1 SRC_DIV# 2 VDD 3 GND 4 SRC_IN 5 SRC_IN# 6 OE0# 7 OE3# 8 DIF_0 9 DIF_0# ...
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ICS9DB803D Eight Output Differential Buffer for PCIe for Gen 2 Pin Description for OE_INV = 1 PIN # PIN NAME PIN TYPE 25 GND DIF_STOP 28 HIGH_BW# 29 DIF_4# 30 DIF_4 31 VDD 32 GND 33 DIF_5# ...
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ICS9DB803D Eight Output Differential Buffer for PCIe for Gen 2 Absolute Max Symbol Parameter VDD_A 3.3V Core Supply Voltage VDD_In 3.3V Logic Supply Voltage V Input Low Voltage IL V Input High Voltage IH Ts Storage Temperature Commerical Operating Range ...
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ICS9DB803D Eight Output Differential Buffer for PCIe for Gen 2 Electrical Characteristics - Input/Supply/Common Output Parameters T = Tambient for the desired operating range, Supply Voltage V A PARAMETER SYMBOL V Input High Voltage IHSE Input Low Voltage V ILSE ...
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ICS9DB803D Eight Output Differential Buffer for PCIe for Gen 2 Electrical Characteristics - DIF 0.7V Current Mode Differential Pair T =Tambient 3.3 V +/-5 PARAMETER SYMBOL Current Source Output Zo Impedance Voltage High VHigh Voltage ...
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ICS9DB803D Eight Output Differential Buffer for PCIe for Gen 2 Clock Periods Differential Outputs with Spread Spectrum Enabled Measurement Window 1 Clock Symbol Lg- Absolute Short-term Period Average Definition Minimum Minimum Absolute Absolute Period Period DIF 100 9.87400 9.99900 DIF ...
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ICS9DB803D Eight Output Differential Buffer for PCIe for Gen 2 Common Recommendations for Differential Routing L1 length, route as non-coupled 50ohm trace L2 length, route as non-coupled 50ohm trace L3 length, route as non-coupled 50ohm trace Rs Rt Down Device ...
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ICS9DB803D Eight Output Differential Buffer for PCIe for Gen 2 Alternative Termination for LVDS and other Common Differential Signals (figure 3) Vdiff Vp-p Vcm 0.45v 0.22v 1.08 0.58 0.28 0.6 0.80 0.40 0.6 0.60 0.3 1.2 R1a = R1b = ...
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ICS9DB803D Eight Output Differential Buffer for PCIe for Gen 2 General SMBus serial interface information for the ICS9DB803D How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address DC • ICS clock will ...
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ICS9DB803D Eight Output Differential Buffer for PCIe for Gen 2 SMBus Table: Frequency Select Register, READ/WRITE ADDRESS (DC/DD) Byte 0 Pin # Name - PD_Mode Bit 7 Bit 6 - STOP_Mode - PD_Polarity Bit 5 - Reserved Bit 4 - ...
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ICS9DB803D Eight Output Differential Buffer for PCIe for Gen 2 SMBus Table: Vendor & Revision ID Register Byte 4 Pin # Name - RID3 Bit 7 - RID2 Bit 6 - RID1 Bit 5 - RID0 Bit 4 - VID3 ...
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ICS9DB803D Eight Output Differential Buffer for PCIe for Gen 2 Note: Polarities in timing diagrams are shown OE_INV = 0. They are similar to OE_INV = 1. PD#, Power Down The PD# pin cleanly shuts off all clocks and places ...
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ICS9DB803D Eight Output Differential Buffer for PCIe for Gen 2 SRC_STOP# The SRC_STOP# signal is an active-low asynchronous input that cleanly stops and starts the DIF outputs. A valid clock must be present on SRC_IN for this input to work ...
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ICS9DB803D Eight Output Differential Buffer for PCIe for Gen 2 SRC_STOP_3 (SRC_Stop = Driven Tristate) SRC_Stop# PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) SRC_STOP_4 (SRC_Stop = Tristate Tristate) SRC_Stop# PWRDWN# DIF (Free ...
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ICS9DB803D Eight Output Differential Buffer for PCIe for Gen INDEX INDEX AREA AREA 45° Eight Output Differential Buffer for PCIe Gen IDT /ICS 48-lead ...
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ICS9DB803D Eight Output Differential Buffer for PCIe for Gen INDEX INDEX AREA AREA Ordering Information Part / Order Number Marking 9DB803DGLF 9DB803DGLF 9DB803DGLFT 9DB803DGLF 9DB803DGILF 9DB803DGILF ...
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ICS9DB803D Eight Output Differential Buffer for PCIe Gen 2 Revision History Rev. Issue Date Description A 8/15/2006 Updated electrical characteristics for final data sheet B Added Input Clock Specs C 2/29/2008 Updated Input Clock Specs D 3/18/2008 Fixed typo in ...