ICS9FG1200DF-1LF IDT, Integrated Device Technology Inc, ICS9FG1200DF-1LF Datasheet - Page 3

• Manufacturer Part Number: ICS9FG1200DF-1LF
• Description: IC FREQUENCY GENERATOR 56-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Frequency Generatorr

Specifications of ICS9FG1200DF-1LF

• Input: Clock
• Output: Differential
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 9FG1200DF-1LF

Pin Description
IDT
PIN # PIN NAME
ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
®
1
2
3
4
5
6
7
8
9
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
HIGH_BW#
CLK_IN
CLK_IN#
SMB_A0
OE0#
DIF_0
DIF_0#
OE1#
DIF_1
DIF_1#
VDD
GND
DIF_2
DIF_2#
OE2#
DIF_3
DIF_3#
OE3#
DIF_4
DIF_4#
OE4#
VDD
GND
DIF_5
DIF_5#
OE5#
SMB_A1
SMBDAT
PIN TYPE
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
DESCRIPTION
3.3V input for selecting PLL Band Width
0 = High, 1= Low
Input for reference clock.
"Complementary" reference clock input.
SMBus address bit 0 (LSB)
Active low input for enabling DIF pair 0.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 1.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 2.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 3.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 4
1 = tri-state outputs, 0 = enable outputs
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 5.
1 = tri-state outputs, 0 = enable outputs
SMBus address bit 1
Data pin of SMBUS circuitry, 5V tolerant
3
1138C 02/08/10