ICS9DB801CGLF IDT, Integrated Device Technology Inc, ICS9DB801CGLF Datasheet - Page 5

• Manufacturer Part Number: ICS9DB801CGLF
• Description: IC BUFFER 8OUTPUT DIFF 48-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Bufferr
• Series: -r

Specifications of ICS9DB801CGLF

• Input: Clock
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Frequency-max: 400MHz
• Number Of Elements: 1
• Supply Current: 200mA
• Pll Input Freq (min): 50MHz
• Pll Input Freq (max): 200MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSSOP
• Output Frequency Range: 50 to 200MHz
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 9DB801CGLF

Pin Description for OE_INV = 1
IDT
PIN #
ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
TM
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
/ICS
TM
Eight Output Differential Buffer for PCI Express (50-200MHz)
BYPASS#/PLL
PIN NAME
SRC_DIV#
SRC_IN#
SRC_IN
DIF_0#
DIF_1#
DIF_2#
DIF_3#
SDATA
OE0#
OE3#
DIF_0
DIF_1
OE1#
OE2#
DIF_2
DIF_3
SCLK
GND
GND
VDD
GND
VDD
VDD
PIN TYPE
OUTPUT 0.7V differential true clock outputs
OUTPUT 0.7V differential complement clock outputs
OUTPUT 0.7V differential true clock outputs
OUTPUT 0.7V differential complement clock outputs
OUTPUT 0.7V differential true clock outputs
OUTPUT 0.7V differential complement clock outputs
OUTPUT 0.7V differential true clock outputs
OUTPUT 0.7V differential complement clock outputs
POWER Power supply, nominal 3.3V
POWER Ground pin.
POWER Ground pin.
POWER Power supply, nominal 3.3V
POWER Ground pin.
POWER Power supply, nominal 3.3V
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
I/O
Active low Input for determining SRC output frequency SRC or
SRC/2.
0 = SRC/2, 1= SRC
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Active low input for enabling DIF pair 0.
1 = tri-state outputs, 0 = enable outputs
Active low input for enabling DIF pair 3.
1 = tri-state outputs, 0 = enable outputs
Active low input for enabling DIF pair 1.
1 = tri-state outputs, 0 = enable outputs
Active low input for enabling DIF pair 2.
1 = tri-state outputs, 0 = enable outputs
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
5
DESCRIPTION
9DB801C
REV E 01/27/11