ICS9DB801CGLF IDT, Integrated Device Technology Inc, ICS9DB801CGLF Datasheet - Page 4

• Manufacturer Part Number: ICS9DB801CGLF
• Description: IC BUFFER 8OUTPUT DIFF 48-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Bufferr
• Series: -r

Specifications of ICS9DB801CGLF

• Input: Clock
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Frequency-max: 400MHz
• Number Of Elements: 1
• Supply Current: 200mA
• Pll Input Freq (min): 50MHz
• Pll Input Freq (max): 200MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSSOP
• Output Frequency Range: 50 to 200MHz
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 9DB801CGLF

Pin Description for OE_INV = 0
IDT
PIN #
ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
TM
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
/ICS
TM
Eight Output Differential Buffer for PCI Express (50-200MHz)
SRC_STOP#
HIGH_BW#
PIN NAME
OE_INV
DIF_4#
DIF_5#
DIF_6#
DIF_7#
GNDA
VDDA
DIF_4
DIF_5
DIF_6
DIF_7
LOCK
OE_5
OE_6
OE_4
OE_7
IREF
GND
GND
PD#
VDD
VDD
PIN TYPE
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
POWER
POWER
POWER
POWER
POWER
POWER
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Ground pin.
Asynchronous active low input pin, with 120Kohm internal pull-
up resistor, used to power down the device. The internal clocks
are disabled and the VCO and the crystal are stopped.
Active low input to stop SRC outputs.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
0.7V differential complement clock outputs
0.7V differential true clock outputs
Power supply, nominal 3.3V
Ground pin.
0.7V differential complement clock outputs
0.7V differential true clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential complement clock outputs
0.7V differential true clock outputs
Power supply, nominal 3.3V
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
0.7V differential complement clock outputs
0.7V differential true clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
3.3V output indicating PLL Lock Status. This pin goes high
when lock is achieved.
This pin establishes the reference current for the differential
current-mode output pairs. This pin requires a fixed precision
resistor tied to ground in order to establish the appropriate
current. 475 ohms is the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
4
DESCRIPTION
9DB801C
REV E 01/27/11