ICS9DB108BGLF IDT, Integrated Device Technology Inc, ICS9DB108BGLF Datasheet - Page 3

IC BUFFER 8OUTPUT DIFF 48-TSSOP

ICS9DB108BGLF

Manufacturer Part Number
ICS9DB108BGLF
Description
IC BUFFER 8OUTPUT DIFF 48-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Bufferr
Series
-r
Datasheet

Specifications of ICS9DB108BGLF

Input
Clock
Output
Clock
Frequency - Max
220MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Frequency-max
220MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
9DB108BGLF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS9DB108BGLF
Manufacturer:
ICS
Quantity:
10
Part Number:
ICS9DB108BGLFT
Manufacturer:
SANYO
Quantity:
4 000
Pin Description (Continued)
0723G—12/02/08
PIN #
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
GND
PD#
SRC_STOP#
HIGH_BW#
DIF_4#
DIF_4
VDD
GND
DIF_5#
DIF_5
OE_5
OE_6
DIF_6#
DIF_6
VDD
GND
DIF_7#
DIF_7
OE_4
OE_7
LOCK
IREF
GNDA
VDDA
Integrated
Circuit
Systems, Inc.
PIN NAME
PIN TYPE
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
Ground pin.
Asynchronous active low input pin used to power down the
device. The internal clocks are disabled and the VCO and the
crystal are stopped.
Active low input to stop diff outputs.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
0.7V differential complement clock outputs
0.7V differential true clock outputs
Power supply, nominal 3.3V
Ground pin.
0.7V differential complement clock outputs
0.7V differential true clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential complement clock outputs
0.7V differential true clock outputs
Power supply, nominal 3.3V
Ground pin.
0.7V differential complement clock outputs
0.7V differential true clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
3.3V output indicating PLL Lock Status. This pin goes high
when lock is achieved.
This pin establishes the reference current for the differential
current-mode output pairs. This pin requires a fixed precision
resistor tied to ground in order to establish the appropriate
current. 475 ohms is the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
3
(Not recommended for new designs)
DESCRIPTION
ICS9DB108

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