ICS9DB401BGLF IDT, Integrated Device Technology Inc, ICS9DB401BGLF Datasheet - Page 5

• Manufacturer Part Number: ICS9DB401BGLF
• Description: IC BUFFER 4OUTPUT DIFF 28-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Buffer/Driverr

Specifications of ICS9DB401BGLF

• Input: Clock
• Output: Clock
• Frequency - Max: 333.33MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Frequency-max: 333.33MHz
• Number Of Elements: 1
• Supply Current: 200mA
• Pll Input Freq (min): 50MHz
• Pll Input Freq (max): 200MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSSOP
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 9DB401BGLF

Absolute Max
1014B—09/07/06
1
2
3
Electrical Characteristics - Input/Supply/Common Output Parameters
T
Tambient
Operating Supply Current
ESD prot
Guaranteed by design and characterization, not 100% tested in production.
See timing diagrams for timing requirements.
Time from deassertion until outputs are >200 mV
Symbol
VDD_In
VDD_A
A
Tcase
Modulation Frequency
Tdrive_SRC_STOP#
= 0 - 70°C; Supply Voltage V
Powerdown Current
V
V
Ts
Input Capacitance
Input High Voltage
Input High Current
Input Low Voltage
Input Low Current
Clk Stabilization
Input Frequency
Input Frequency
Input Frequency
IL
IH
Pin Inductance
PLL Bandwidth
PARAMETER
Tdrive_PD#
Integrated
Circuit
Systems, Inc.
Trise
Tfall
3.3V Logic Supply Voltage
3.3V Core Supply Voltage
Ambient Operating Temp
Storage Temperature
Input ESD protection
human body model
Input High Voltage
Case Temperature
Input Low Voltage
1,2
1
1
Parameter
I
SYMBOL
DD3.3ByPass
I
I
F
F
DD3.3PLL
fMOD
DD3.3PD
T
C
F
iBypass
iBypass
BW
DD
L
C
V
V
I
I
STAB
I
iPLL
OUT
IL1
IL2
IH
pin
IH
IL
IN
= 3.3 V +/-5%
V
Bypass Mode (Revision B/REV
Bypass Mode (Revision C/REV
From V
input clock stabilization or de-
IN
assertion of PD# to 1st clock
V
all differential pairs tri-stated
Full Active, C
IN
SRC_Stop# de-assertion
= 0 V; Inputs with no pull-up
Output pin capacitance
DIF output enable after
DIF output enable after
Triangular Modulation
= 0 V; Inputs with pull-up
PLL Bandwidth when
PLL Bandwidth when
Rise time of PD# and
Fall time of PD# and
GND-0.5
all diff pairs driven
PD# de-assertion
2000
Min
DD
-65
CONDITIONS
SRC_STOP#
SRC_STOP#
0
Logic Inputs
3.3 V +/-5%
3.3 V +/-5%
PLL_BW=0
PLL_BW=1
PLL Mode
Power-Up and after
V
resistors
resistors
ID = 1H)
ID = 2H)
IN
= V
L
= Full load;
DD
V
DD
Max
150
115
4.6
4.6
+0.5V
70
5
GND - 0.3
Units
-200
°
°C
°C
MIN
V
V
V
V
V
C
1.5
2.4
0.7
50
30
-5
-5
2
0
0
TYP
175
160
0.5
10
3
1
V
333.33
DD
MAX
200
175
200
400
300
0.8
3.4
1.4
40
33
15
5
4
7
4
4
1
5
5
+ 0.3
UNITS NOTES
MHz
MHz
MHz
MHz
MHz
kHz
mA
mA
mA
mA
nH
ms
uA
uA
uA
pF
pF
ns
us
ns
ns
ICS9DB401
V
V
1,2
1,3
1,3
1
1
1
1
1
1
1
2