ICS94228BFLFT IDT, Integrated Device Technology Inc, ICS94228BFLFT Datasheet - Page 15

• Manufacturer Part Number: ICS94228BFLFT
• Description: IC CLOCK CHIP PROGR AMDK7 48SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Frequency Generatorr

Specifications of ICS94228BFLFT

• Input: Crystal
• Output: Clock
• Frequency - Max: 233.33MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Frequency-max: 233.33MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 94228BFLFT

Notes:
1. All timing is referenced to the internal CPUCLK.
2. AGP_STOP# is an asynchronous input and metastable conditions
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
5. Only applies if MODE pin latched 0 at power up.
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power
operation. CPU_STOP# is synchronized by the ICS94228. All other clocks will continue to run while the CPUCLKs
clocks are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees
the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than
4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
0447E—05/07/04
AGP_STOP# Timing Diagram
AGP_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the AGP clocks. for low power
operation. AGP_STOP# is synchronized by the ICS94228. The AGPCLKs will always be stopped in a low state and
start in such a manner that guarantees the high pulse width is a full pulse. AGPCLK on latency is less than AGPCLK
and AGPCLK off latency is less than 3 AGPCLKs. This function is available only with MODE pin latched low.
may exist. This signal is synchronized to the CPUCLKs inside the
ICS4228.
synchronized to the CPUCLKs inside the ICS94228.
CPUCLKC_CSC
CPUCLKT_CST
CPU_STOP#
INTERNAL
PD# (High)
CPUCLKT
CPUCLKC
CPUCLK
PCICLK
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ICS94228