ICS94228BFLFT IDT, Integrated Device Technology Inc, ICS94228BFLFT Datasheet

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ICS94228BFLFT

Manufacturer Part Number
ICS94228BFLFT
Description
IC CLOCK CHIP PROGR AMDK7 48SSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Frequency Generatorr
Datasheet

Specifications of ICS94228BFLFT

Input
Crystal
Output
Clock
Frequency - Max
233.33MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-SSOP
Frequency-max
233.33MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
94228BFLFT
Programmable System Clock Chip for AMD - K7™ processor
Recommended Application:
VIA KT266 style chipset
Output Features:
Features:
Skew Specifications:
Block Diagram
CPU_STOP#
0447E—05/07/04
AGP_STOP#
REF_STOP#
PCI_STOP#
SEL24_48#
FS (3:0)
1 - Differential pair open drain CPU clocks @ 2.7V
1 - Differential pair push-pull CPU clocks @ 2.5V
11 - PCI including 1 free running and 1 early @ 3.3V
1 - 48MHz, @ 3.3V fixed
1 - 24/48MHz @ 3.3V
3 - REF @ 3.3V, 14.318MHz.
Programmable output frequency.
Programmable output rise/fall time.
Programmable slew and skew control for CPUCLK,
PCICLK, AGP, REF, 48MHz and 24_48MHz.
Real time system reset output.
Spread spectrum for EMI control typically
by 7dB to 8dB, with programmable spread
percentage.
Watchdog timer technology to reset system
if over-clocking causes malfunction.
Uses external 14.318MHz crystal.
CPU - CPU: <200ps
PCI - PCI: <500ps
CPU (early - PCI: min=1.0ns, max=2.6ns
CPU cycle to cycle jitter: <250ps
SDATA
SCLK
PD#
X2
X1
XTAL
OSC
Spectrum
PLL2
Spread
Control
Config.
PLL1
Logic
Reg.
Integrated
Circuit
Systems, Inc.
DIVDER
DIVDER
DIVDER
DIVDER
CPU
CPU
AGP
PCI
/ 2
Stop
Stop
Stop
Stop
9
3
2
2
48MHz (1:0)
24_48MHz
REF_F
PCICLK9_E
PCICLK (8:0)
PCICLK_F
AGP (2:0)
SRESET#
REF (1:0)
CPUCLKC0
CPUCLK_CSC0
CPUCLKT0
CPUCLK_CST0
*SEL24_48#/PCICLK0
Functionality
F
S
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
*FS3/24_48MHz
3
*FS2/48MHz
PCICLK9_E
* Internal Pull-up Resistor of 120K to VDD
PCICLK_F
F
SRESET#
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
PCICLK7
PCILCK8
VDDREF
S
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
AVDD48
VDDPCI
VDDPCI
2
GND
GND
GND
GND
X1
X2
F
0
0
0
0
0
0
0
0
S
1
1
1
1
1
1
1
1
1
48-Pin 300mil SSOP
Pin Configuration
F
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
S
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
2
2
2
1
1
1
1
1
1
1
1
1
1
2
2
(
6
C
M
1
0
0
3
2
9
8
7
5
4
2
1
6
0
3
6
0
0
0
3
0
0
0
0
0
0
0
0
6
0
3
P
H
6 .
3 .
0 .
0 .
0 .
0 .
0 .
0 .
0 .
0 .
0 .
0 .
0 .
6 .
0 .
3 .
U
) z
7
3
0
0
0
0
0
0
0
0
0
0
0
7
0
3
ICS94228
(
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
7
6
7
7
6
7
7
6
6
6
6
6
6
6
7
7
A
M
0
6
6
2
8
5
0
0
6
6
6
6
6
6
7
3
G
H
7 .
3 .
0 .
6 .
0 .
0 .
0 .
0 .
0 .
0 .
0 .
6 .
6 .
6 .
6 .
6 .
P
) z
8
3
0
7
0
0
0
0
0
0
0
7
7
7
7
7
REF0/
REF1/FS1*
REF_F
REF_STOP#*
AGP_STOP#*
GND
CPUCLKT0
CPUCLKC0
VDDL
CPUCLK_CST0
CPUCLK_CSC0
GND
CPU_STOP#*
PCI_STOP#*
PD#*
AVDD
AGND
SDATA
SCLK
GND
AGP2
AGP1
AGP0
VDDAGP
P
(
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
C
M
FS0*
8
6
5
3
8
6
4
7
5
0
3
3
3
3
3
3
I
C
H
8 .
6 .
0 .
3 .
0 .
0 .
0 .
5 .
0 .
0 .
0 .
3 .
3 .
3 .
3 .
3 .
) z
L
8
7
0
3
0
0
0
0
0
0
0
3
3
3
3
3
K

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ICS94228BFLFT Summary of contents

Page 1

Integrated Circuit Systems, Inc. Programmable System Clock Chip for AMD - K7™ processor Recommended Application: VIA KT266 style chipset Output Features: • Differential pair open drain CPU clocks @ 2.7V • Differential pair push-pull CPU clocks ...

Page 2

ICS94228 Pin Descriptions ...

Page 3

General Description The ICS94228 is a main clock synthesizer chip for AMD-K7 based systems with VIA style chipset. This provides all clocks required for such a system. The ICS94228 belongs to ICS new generation of programmable system clock generators. 2 ...

Page 4

ICS94228 2 General I C serial interface information for the ICS94228 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends a dummy ...

Page 5

Brief I Programmable System Frequency Generator Register Name Functionality & Frequency Select Register Output Control Registers Vendor ID & Revision ID Registers Byte Count Read Back Register Watchdog Enable Register Watchdog Control Registers VCO Control Selection Bit VCO Frequency ...

Page 6

ICS94228 Serial Configuration Command Bitmap Byte0: Functionality and Frequency Select Register (default = 0) Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SSB1 SSB0 FS3 FS2 FS1 FS0 ...

Page 7

Byte 1: CPU, Active/Inactive Register (1= enable disable ...

Page 8

ICS94228 Byte 7: Vendor ID2, Active/Inactive Register (1= enable disable ...

Page 9

Byte 13: Output Skew Control Register (1= enable disable ...

Page 10

ICS94228 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Logic Inputs . . . . . . ...

Page 11

Electrical Characteristics - REF 70° 3.3 V +/-5 PARAMETER SYMBOL Output High Voltage V OH5 Output Low Voltage V OL5 Output High Current I OH5 Output Low Current I OL5 1 ...

Page 12

ICS94228 Electrical Characteristics - PCICLK 70°C; VDD = 3.3 V +/-5 (unless otherwise stated) A PARAMETER SYMBOL Output High Voltage V OH1 Output Low Voltage V Output High Current I OH1 Output ...

Page 13

Electrical Characteristics - 24MHz, 48MHz 70°C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5 (unless otherwise stated) A PARAMETER SYMBOL Output High Voltage Output Low Voltage Output High Current Output ...

Page 14

ICS94228 Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) on the ICS94228 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on ...

Page 15

AGP_STOP# Timing Diagram AGP_STOP asychronous input to the clock synthesizer used to turn off the AGP clocks. for low power operation. AGP_STOP# is synchronized by the ICS94228. The AGPCLKs will always be stopped in a low ...

Page 16

ICS94228 PD# Timing Diagram The power down selection is used to put the part into a very low power state without turning off the power to the part. PD asynchronous active low input. This signal needs to be ...

Page 17

INDEX INDEX AREA AREA 45° 45° SEATING SEATING b PLANE PLANE .10 (.004) C .10 (.004) C 300 mil SSOP Package Ordering Information ICS94228yFLF-T Example: ...

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