ICS94228BFLFT IDT, Integrated Device Technology Inc, ICS94228BFLFT Datasheet - Page 14

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ICS94228BFLFT

Manufacturer Part Number
ICS94228BFLFT
Description
IC CLOCK CHIP PROGR AMDK7 48SSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Frequency Generatorr
Datasheet

Specifications of ICS94228BFLFT

Input
Crystal
Output
Clock
Frequency - Max
233.33MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-SSOP
Frequency-max
233.33MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
94228BFLFT
0447E—05/07/04
The I/O pins designated by (input/output) on the ICS94228
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and
stored into a 5-bit internal data latch. At the end of Power-
On reset, (see AC characteristics for timing values), the
device changes the mode of operations for these pins to
an output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Shared Pin Operation -
Input/Output Pins
ICS94228
Device
Pad
Programming
Header
Via to Gnd
Series Term. Res.
Fig. 1
14
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor.
8.2K
2K
Clock trace to load
Via to
VDD

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