ICS950410AFLFT IDT, Integrated Device Technology Inc, ICS950410AFLFT Datasheet

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ICS950410AFLFT

Manufacturer Part Number
ICS950410AFLFT
Description
IC SYSTEM CLK CHIP AMD-K8 48SSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Timing Control Hubr
Datasheet

Specifications of ICS950410AFLFT

Input
Crystal
Output
Clock
Frequency - Max
300MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-SSOP
Frequency-max
300MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
950410AFLFT
AMD - K8™ System Clock Chip
Recommended Application:
AMD K8 System Clock with AMD, VIA or ALI Chipset
Output Features:
Features:
Functionality
0888A—04/22/05
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to
change without notice.
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
3 - Differential pair push-pull CPU clocks @
3.3V
9 - PCICLK (Including 1 free running) @ 3.3V
3 - Selectable PCICLK/HTTCLK @ 3.3V
1 - HTTCLK @ 3.3V
1 - 48MHz @ 3.3V fixed.
1 - 24/48MHz @ 3.3V
2 - REF @ 3.3V, 14.318MHz.
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI
control.
Watchdog timer technology and RESET# output
to reset system
if system malfunctions.
Programmable watch dog safe frequency.
Support I
write operations.
Uses external 14.318MHz crystal.
Supports Hyper Transport Technology (HTTCLK).
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
2
FS1
C Index read/write and block read/
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Integrated
Circuit
Systems, Inc.
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
100.90
133.90
168.00
202.00
100.20
133.50
166.70
200.40
150.00
180.00
210.00
240.00
270.00
233.33
266.67
300.00
CPU
MHz
67.27
66.95
67.20
67.33
66.80
66.75
66.68
66.80
60.00
60.00
70.00
60.00
67.50
66.67
66.67
75.00
MHz
HTT
33.63
33.48
33.60
33.67
33.40
33.38
33.34
33.40
30.00
30.00
35.00
30.00
33.75
33.33
33.33
37.50
MHz
PCI
*ModeB/PCICLK8/HTTCLK1 7
2X
PCICLK11/HTTCLK3 11
PCICLK9/HTTCLK2 8
This Output has 2X Default Drive and can be programmaed lower via IIC
*ModeA/HTTCLK0 6
*FS2/PCICLK10 12
~*FS0/REF0 1
2X
2X
2X
2X
PCICLK0 13
PCICLK1 14
PCICLK2 17
PCICLK3 18
PCICLK4 21
PCICLK5 22
PCICLK6 23
PCICLK7 24
VDDHTT 2
VDDPCI 9
VDDPCI 16
VDDPCI 19
GND 5
GND 10
GND 15
GND 20
Preliminary Product Preview
X1 3
X2 4
~ This Output has 1.5x drive
Pin Configuration
* Internal Pull-Up Resistor
48-SSOP
48 REF1/FS1*
47 GND
46 VDDREF
45 Reset#
44 VDDA
43 GND
42 CPUCLK8T0
41 CPUCLK8C0
40 VDDCPU
39 CPUCLK8T1
38 CPUCLK8C1
37 GND
36 VDDCPU
35 CPUCLK8T2
34 CPUCLK8C2
33 GND
32 Turbo#
31 PD#*
30 48MHz/FS3**
29 GND
28 AVDD48
27 24_48MHz/Sel24_48#*
26 SDATA
25 SCLK
ICS950410

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ICS950410AFLFT Summary of contents

Page 1

Integrated Circuit Systems, Inc. AMD - K8™ System Clock Chip Recommended Application: AMD K8 System Clock with AMD, VIA or ALI Chipset Output Features: • Differential pair push-pull CPU clocks @ 3.3V • PCICLK (Including 1 ...

Page 2

ICS950410 Preliminary Product Preview Pin Descriptions PIN PIN # PIN NAME TYPE 1 I/O ~*FS0/REF0 2 VDDHTT PWR OUT 5 GND PWR 6 *ModeA/HTTCLK0 I/O 7 *ModeB/PCICLK8/HTTCLK1 I/O 8 PCICLK9/HTTCLK2 OUT 9 VDDPCI PWR 10 ...

Page 3

General Description The ICS950410 is a main system clock solution for desktop designs using the AMD K8 CPU. It provides all necessary clock signals for Clawhammer and Sledgehammer with AMD, VIA or ALI systems. The ICS950410 is part of a ...

Page 4

ICS950410 Preliminary Product Preview Table1: Frequency Selection Table Bit4 Bit3 Bit2 Bit1 Bit0 CPU FS4 FS3 FS2 FS1 FS0 MHz 100. 133. 168. ...

Page 5

General I How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ICS clock will acknowledge ...

Page 6

ICS950410 Preliminary Product Preview Table: Frequency Select Register Byte 0 Pin # - SS_EN Bit 7 - SEL24_48MHz Bit Source Select Bit 5 - Bit 4 - Bit 3 - Bit 2 - Bit ...

Page 7

I C Table: Output Control Register Byte 4 Pin # - Bit 7 - Bit 6 - Bit 5 - Bit 4 - Bit 3 - Bit 2 - Bit 1 - Bit Table: Reserved ...

Page 8

ICS950410 Preliminary Product Preview Table: Skew Control Register Byte 8 Pin # - PCI/HTTSkw3 Bit 7 - PCI/HTTSkw2 Bit 6 - PCI/HTTSkw1 Bit 5 - PCI/HTTSkw0 Bit 4 - PCISkw3 Bit 3 - PCISkw2 Bit 2 - ...

Page 9

I C Table: VCO Frequency Control Register Byte 12 Pin # - N Div7 Bit Div6 Bit Div5 Bit Div4 Bit Div3 Bit Div2 ...

Page 10

ICS950410 Preliminary Product Preview Absolute Maximum Rating PARAMETER SYMBOL 3.3V Core Supply Voltage VDD_A 3.3V Logic Input Supply VDD_In Voltage Storage Temperature Ts Ambient Operating Temp Tambient Case Temperature Tcase Input ESD protection HBM ESD prot 1 Guaranteed by design ...

Page 11

Electrical Characteristics - PCICLK/PCICLK_F PARAMETER SYMBOL Output Impedance R DSP Output High Voltage V OH Output Low Voltage V OL Output High Current I OH Output Low Current I OL Edge Rate t slewr/f Rise Time t r Fall Time ...

Page 12

ICS950410 Preliminary Product Preview Electrical Characteristics - CPUCLKK8T/C K8 3.3V Push Pull Differential Pair PARAMETER SYMBOL δ V /δ t Rising Edge Rate δ V /δ t Falling Edge Rate Differential Voltage V DIFF ∆ V Change in V Magnitude ...

Page 13

Electrical Characteristics - REF-14.318MHz PARAMETER SYMBOL Long Accuracy ppm Clock period T period Output High Voltage V OH Output Low Voltage V OL Output High Current I OH Output Low Current I OL Edge Rate t slewr/f Rise Time t ...

Page 14

ICS950410 Preliminary Product Preview Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) on the ICS950410 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that ...

Page 15

INDEX INDEX AREA AREA 45° 45° SEATING SEATING b PLANE PLANE .10 (.004) C .10 (.004) C 300 mil SSOP Package Ordering Information ICS950410yFLF-T Example: ...

Page 16

ICS950410 Preliminary Product Preview Revision History Rev. Issue Date Description 1. Updated Byte 11/12 M/N programming description 2. Updated Ordering Information from "Lead Free" to Annealed Lead Free". A 4/22/2005 3. Preliminary Release. 0888A—04/22/05 16 Page # 8-9,15 ...

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